drm/amd/display: add valid regoffset and NULL pointer check

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 8eb8b876846599aa07b030516161fc6b14f20f03..fa56c0fc02bf512ccc67ba15413c8521d6ad41b9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -33,6 +33,7 @@
 #include "dc_link_dp.h"
 #include "dc_link_ddc.h"
 #include "link_hwss.h"
+#include "opp.h"
 
 #include "link_encoder.h"
 #include "hw_sequencer.h"
@@ -2382,9 +2383,10 @@ void core_link_enable_stream(
        core_dc->hwss.enable_audio_stream(pipe_ctx);
 
        /* turn off otg test pattern if enable */
-       pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
-                       CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
-                       COLOR_DEPTH_UNDEFINED);
+       if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
+               pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
+                               CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+                               COLOR_DEPTH_UNDEFINED);
 
        core_dc->hwss.enable_stream(pipe_ctx);
 

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 509f265663d2727a6a5fecdd2903ddac2fbcc94f..049fc5cce1d26d07078174aec4e9e7ed2764df54 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3,6 +3,7 @@
 #include "dc.h"
 #include "dc_link_dp.h"
 #include "dm_helpers.h"
+#include "opp.h"
 
 #include "inc/core_types.h"
 #include "link_hwss.h"
@@ -2511,8 +2512,8 @@ static void set_crtc_test_pattern(struct dc_link *link,
                pipe_ctx->stream->bit_depth_params = params;
                pipe_ctx->stream_res.opp->funcs->
                        opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
-
-               pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
+               if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
+                       pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
                                controller_test_pattern, color_depth);
        }
        break;
@@ -2524,8 +2525,8 @@ static void set_crtc_test_pattern(struct dc_link *link,
                pipe_ctx->stream->bit_depth_params = params;
                pipe_ctx->stream_res.opp->funcs->
                        opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
-
-               pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
+               if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
+                       pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
                                CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
                                color_depth);
        }

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 3b983b3f342342cd55f9e5b80d11d91577f0abe3..9cbd5036db0794868a57bcf034bb3cec8899c3fd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1475,7 +1475,7 @@ static void power_down_controllers(struct dc *dc)
 {
        int i;
 
-       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+       for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
                dc->res_pool->timing_generators[i]->funcs->disable_crtc(
                                dc->res_pool->timing_generators[i]);
        }
@@ -1515,12 +1515,13 @@ static void disable_vga_and_power_gate_all_controllers(
        struct timing_generator *tg;
        struct dc_context *ctx = dc->ctx;
 
-       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+       for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
                tg = dc->res_pool->timing_generators[i];
 
                if (tg->funcs->disable_vga)
                        tg->funcs->disable_vga(tg);
-
+       }
+       for (i = 0; i < dc->res_pool->pipe_count; i++) {
                /* Enable CLOCK gating for each pipe BEFORE controller
                 * powergating. */
                enable_display_pipe_clock_gating(ctx,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index 623db09389b5c5082dd8a487e7307779b6302e54..1ea91e153d3a6b05caebdce7291cda3e4b889495 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -483,6 +483,11 @@ void hubbub1_update_dchub(
        struct hubbub *hubbub,
        struct dchub_init_data *dh_data)
 {
+       if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) {
+               ASSERT(false);
+               /*should not come here*/
+               return;
+       }
        /* TODO: port code from dal2 */
        switch (dh_data->fb_mode) {
        case FRAME_BUFFER_MODE_ZFB_ONLY:

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 21b45e8d49f7ddd1d331318d4d065cc0153b0811..3b2cb2d3b8a61f6fb2c55bfb427a06d747c2d1f1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -415,6 +415,8 @@ static void dpp_pg_control(
 
        if (hws->ctx->dc->debug.disable_dpp_power_gate)
                return;
+       if (REG(DOMAIN1_PG_CONFIG) == 0)
+               return;
 
        switch (dpp_inst) {
        case 0: /* DPP0 */
@@ -465,6 +467,8 @@ static void hubp_pg_control(
 
        if (hws->ctx->dc->debug.disable_hubp_power_gate)
                return;
+       if (REG(DOMAIN0_PG_CONFIG) == 0)
+               return;
 
        switch (hubp_inst) {
        case 0: /* DCHUBP0 */
@@ -865,7 +869,8 @@ void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
                return;
 
        mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
-       opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
+       if (opp != NULL)
+               opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
 
        dc->optimized_required = true;
 
@@ -1343,10 +1348,11 @@ static void dcn10_enable_per_frame_crtc_position_reset(
 
        DC_SYNC_INFO("Setting up\n");
        for (i = 0; i < group_size; i++)
-               grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
-                               grouped_pipes[i]->stream_res.tg,
-                               grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
-                               &grouped_pipes[i]->stream->triggered_crtc_reset);
+               if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)
+                       grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
+                                       grouped_pipes[i]->stream_res.tg,
+                                       grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
+                                       &grouped_pipes[i]->stream->triggered_crtc_reset);
 
        DC_SYNC_INFO("Waiting for trigger\n");
 
@@ -2496,8 +2502,14 @@ static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
 
 static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
 {
-       if (hws->ctx->dc->res_pool->hubbub != NULL)
-               hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
+       if (hws->ctx->dc->res_pool->hubbub != NULL) {
+               struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0];
+
+               if (hubp->funcs->hubp_update_dchub)
+                       hubp->funcs->hubp_update_dchub(hubp, dh_data);
+               else
+                       hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
+       }
 }
 
 static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)