drm/amd/pp: Delete is_smc_ram_running function on RV
authorRex Zhu <Rex.Zhu@amd.com>
Wed, 7 Mar 2018 05:32:45 +0000 (13:32 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 15 Mar 2018 14:56:11 +0000 (09:56 -0500)
1. There is a race condition when another ip also use same register pairs
2. check once at boot up by GetDriverIfVersion message is sufficient
   to check SMU health. so delete is_smc_ram_running check.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h

index ac3350af93745e6d1cc54de1463562def46be7b4..68cfb999521a32b7fe67af6304aae9cb027e8ede 100644 (file)
 #define smnMP1_FIRMWARE_FLAGS       0x3010028
 
 
-bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr)
-{
-       uint32_t mp1_fw_flags, reg;
-
-       reg = soc15_get_register_offset(NBIF_HWID, 0,
-                       mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
-
-       cgs_write_register(hwmgr->device, reg,
-                       (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
-
-       reg = soc15_get_register_offset(NBIF_HWID, 0,
-                       mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
-
-       mp1_fw_flags = cgs_read_register(hwmgr->device, reg);
-
-       if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
-               return true;
-
-       return false;
-}
-
 static uint32_t rv_wait_for_response(struct pp_hwmgr *hwmgr)
 {
        uint32_t reg;
 
-       if (!rv_is_smc_ram_running(hwmgr))
-               return -EINVAL;
-
        reg = soc15_get_register_offset(MP1_HWID, 0,
                        mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
 
@@ -89,9 +65,6 @@ int rv_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
 {
        uint32_t reg;
 
-       if (!rv_is_smc_ram_running(hwmgr))
-               return -EINVAL;
-
        reg = soc15_get_register_offset(MP1_HWID, 0,
                        mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
        cgs_write_register(hwmgr->device, reg, msg);
index 0ff4ac5838f7831b81e2d50ed184912c59dc4bfa..401265cb548a1ef2ca5109055a320e2ca6d3464c 100644 (file)
@@ -51,7 +51,6 @@ struct rv_smumgr {
 };
 
 int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
-bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr);
 int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
                uint8_t *table, int16_t table_id);
 int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,