drm/i915: Align intel_dsi*.c files a bit

I'm not really that insisting on checkpath compliance, but ragged
function paramter alignment does get me. Please adjust your editor to
just do this for you.

Cc: Shobhit Kumar <shobhit.kumar@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index aea8f3383c2696919d7eeb456d6bc6c6520b7104..5bd9e09ad3c5ddac4202a6f21e6fb7198572ffb2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -184,7 +184,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 
        /* update the hw state for DPLL */
        intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
-                                               DPLL_REFA_CLK_ENABLE_VLV;
+               DPLL_REFA_CLK_ENABLE_VLV;
 
        tmp = I915_READ(DSPCLK_GATE_D);
        tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
@@ -259,8 +259,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
        temp = I915_READ(MIPI_CTRL(pipe));
        temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
        I915_WRITE(MIPI_CTRL(pipe), temp |
-                       intel_dsi->escape_clk_div <<
-                       ESCAPE_CLOCK_DIVIDER_SHIFT);
+                  intel_dsi->escape_clk_div <<
+                  ESCAPE_CLOCK_DIVIDER_SHIFT);
 
        I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP);
 
@@ -297,7 +297,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
        usleep_range(2000, 2500);
 
        if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
-                                       == 0x00000), 30))
+                     == 0x00000), 30))
                DRM_ERROR("DSI LP not going Low\n");
 
        val = I915_READ(MIPI_PORT_CTRL(pipe));
@@ -427,7 +427,7 @@ static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
                       u16 burst_mode_ratio)
 {
        return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
-                                                       8 * 100), lane_count);
+                                        8 * 100), lane_count);
 }
 
 static void set_dsi_timings(struct drm_encoder *encoder,
@@ -454,10 +454,10 @@ static void set_dsi_timings(struct drm_encoder *encoder,
 
        /* horizontal values are in terms of high speed byte clock */
        hactive = txbyteclkhs(hactive, bpp, lane_count,
-                                               intel_dsi->burst_mode_ratio);
+                             intel_dsi->burst_mode_ratio);
        hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
        hsync = txbyteclkhs(hsync, bpp, lane_count,
-                                               intel_dsi->burst_mode_ratio);
+                           intel_dsi->burst_mode_ratio);
        hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 
        I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
@@ -582,7 +582,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
         * XXX: write MIPI_STOP_STATE_STALL?
         */
        I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
-                                               intel_dsi->hs_to_lp_count);
+                  intel_dsi->hs_to_lp_count);
 
        /* XXX: low power clock equivalence in terms of byte clock. the number
         * of byte clocks occupied in one low power clock. based on txbyteclkhs
@@ -607,10 +607,10 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
                 * 64 like 1366 x 768. Enable RANDOM resolution support for such
                 * panels by default */
                I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
-                               intel_dsi->video_frmt_cfg_bits |
-                               intel_dsi->video_mode_format |
-                               IP_TG_CONFIG |
-                               RANDOM_DPI_DISPLAY_RESOLUTION);
+                          intel_dsi->video_frmt_cfg_bits |
+                          intel_dsi->video_mode_format |
+                          IP_TG_CONFIG |
+                          RANDOM_DPI_DISPLAY_RESOLUTION);
 }
 
 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)

diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 7f1430ac8543617e5cc1788c98be97836ef85771..f4767fd2ebeb0ea9d60c971de76a164c459a5ef8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -430,7 +430,7 @@ void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi)
        u32 mask;
 
        mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
-                                       LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
+               LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
 
        if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 100))
                DRM_ERROR("DPI FIFOs are not empty\n");

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 06fad93a68c8781ba7295c0da5c9124453c972a0..fa7a6ca34cd654bb7c66665c4c80235b28ea2673 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -190,7 +190,7 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
        for (m = 62; m <= 92; m++) {
                for (p = 2; p <= 6; p++) {
                        /* Find the optimal m and p divisors
-                       with minimal error +/- the required clock */
+                          with minimal error +/- the required clock */
                        calc_dsi_clk = (m * ref_clk) / p;
                        if (calc_dsi_clk == target_dsi_clk) {
                                calc_m = m;
@@ -233,7 +233,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
        u32 dsi_clk;
 
        dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
-                                               intel_dsi->lane_count);
+                                   intel_dsi->lane_count);
 
        ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
        if (ret) {
@@ -315,8 +315,8 @@ static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
        }
 
        WARN(bpp != pipe_bpp,
-               "bpp match assertion failure (expected %d, current %d)\n",
-               bpp, pipe_bpp);
+            "bpp match assertion failure (expected %d, current %d)\n",
+            bpp, pipe_bpp);
 }
 
 u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)