CONFIG_BCM7038_L1_IRQ=y
CONFIG_BCM7038_WDT=y
CONFIG_BCM7120_L2_IRQ=y
+CONFIG_BCMA=y
+CONFIG_BCMA_BLOCKIO=y
+# CONFIG_BCMA_DEBUG is not set
+# CONFIG_BCMA_DRIVER_GMAC_CMN is not set
+# CONFIG_BCMA_DRIVER_MIPS is not set
+CONFIG_BCMA_DRIVER_PCI=y
+# CONFIG_BCMA_DRIVER_PCI_HOSTMODE is not set
+CONFIG_BCMA_HOST_PCI=y
+CONFIG_BCMA_HOST_PCI_POSSIBLE=y
+# CONFIG_BCMA_HOST_SOC is not set
+CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BMIPS_GENERIC=y
CONFIG_BOARD_SCACHE=y
CONFIG_MDIO_BUS_MUX=y
CONFIG_MDIO_BUS_MUX_BCM6368=y
CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
CONFIG_MEMFD_CREATE=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
CONFIG_OF_MDIO=y
CONFIG_OF_NET=y
CONFIG_PADATA=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_BCM6318=y
+CONFIG_PCIE_BCM6328=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_BCM6348=y
+CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DRIVERS_LEGACY=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SRCU=y
+CONFIG_SSB=y
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_BLOCKIO=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_SPROM=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_SWPHY=y
CONFIG_SYNC_R4K=y
status = "okay";
};
+&pcie {
+ status = "okay";
+};
+
&pinctrl {
pinctrl_leds: leds {
function = "led";
status = "disabled";
};
+ pcie: pcie@10010000 {
+ compatible = "brcm,bcm6318-pcie";
+ reg = <0x10010000 0x10000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ bus-range = <0x00 0x01>;
+ ranges = <0x2000000 0 0x10200000 0x10200000 0 0x100000>;
+ linux,pci-probe-only = <1>;
+
+ interrupt-parent = <&periph_intc>;
+ interrupts = <BCM6318_IRQ_PCIE_RC>;
+
+ clocks = <&periph_clk BCM6318_CLK_PCIE>,
+ <&periph_clk BCM6318_CLK_PCIE25>,
+ <&ubus_clk BCM6318_UCLK_PCIE>;
+ clock-names = "pcie",
+ "pcie25",
+ "pcie-ubus";
+
+ resets = <&periph_rst BCM6318_RST_PCIE>,
+ <&periph_rst BCM6318_RST_PCIE_EXT>,
+ <&periph_rst BCM6318_RST_PCIE_CORE>,
+ <&periph_rst BCM6318_RST_PCIE_HARD>;
+ reset-names = "pcie",
+ "pcie-ext",
+ "pcie-core",
+ "pcie-hard";
+
+ power-domains = <&periph_pwr BCM6318_POWER_DOMAIN_PCIE>;
+
+ status = "disabled";
+ };
+
switch0: switch@10080000 {
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
+ serdes_cntl: syscon@10001804 {
+ compatible = "syscon";
+ reg = <0x10001804 0x4>;
+ native-endian;
+ };
+
periph_pwr: power-controller@1000184c {
compatible = "brcm,bcm63268-power-controller";
reg = <0x1000184c 0x4>;
status = "disabled";
};
+ pcie: pcie@106e0000 {
+ compatible = "brcm,bcm6328-pcie";
+ reg = <0x106e0000 0x10000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ bus-range = <0x00 0x01>;
+ ranges = <0x2000000 0 0x11000000 0x11000000 0 0xf00000>;
+ linux,pci-probe-only = <1>;
+
+ interrupt-parent = <&periph_intc>;
+ interrupts = <BCM63268_IRQ_PCIE_RC>;
+
+ clocks = <&periph_clk BCM63268_CLK_PCIE>;
+ clock-names = "pcie";
+
+ resets = <&periph_rst BCM63268_RST_PCIE>,
+ <&periph_rst BCM63268_RST_PCIE_EXT>,
+ <&periph_rst BCM63268_RST_PCIE_CORE>,
+ <&periph_rst BCM63268_RST_PCIE_HARD>;
+ reset-names = "pcie",
+ "pcie-ext",
+ "pcie-core",
+ "pcie-hard";
+
+ power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_PCIE>;
+
+ brcm,serdes = <&serdes_cntl>;
+
+ status = "disabled";
+ };
+
switch0: switch@10700000 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
+&pcie {
+ status = "okay";
+};
+
&pinctrl {
pinctrl_leds: leds {
function = "led";
status = "disabled";
};
+ serdes_cntl: syscon@10001800 {
+ compatible = "syscon";
+ reg = <0x10001800 0x4>;
+ native-endian;
+ };
+
periph_pwr: power-controller@10001848 {
compatible = "brcm,bcm6328-power-controller";
reg = <0x10001848 0x4>;
reg = <1>;
};
};
+
+ pcie: pcie@10e40000 {
+ compatible = "brcm,bcm6328-pcie";
+ reg = <0x10e40000 0x10000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ bus-range = <0x00 0x01>;
+ ranges = <0x2000000 0 0x10f00000 0x10f00000 0 0x100000>;
+ linux,pci-probe-only = <1>;
+
+ interrupt-parent = <&periph_intc>;
+ interrupts = <BCM6328_IRQ_PCIE_RC>;
+
+ clocks = <&periph_clk BCM6328_CLK_PCIE>;
+ clock-names = "pcie";
+
+ resets = <&periph_rst BCM6328_RST_PCIE>,
+ <&periph_rst BCM6328_RST_PCIE_EXT>,
+ <&periph_rst BCM6328_RST_PCIE_CORE>,
+ <&periph_rst BCM6328_RST_PCIE_HARD>;
+ reset-names = "pcie",
+ "pcie-ext",
+ "pcie-core",
+ "pcie-hard";
+
+ power-domains = <&periph_pwr BCM6328_POWER_DOMAIN_PCIE>;
+
+ brcm,serdes = <&serdes_cntl>;
+
+ status = "disabled";
+ };
};
};
status = "okay";
};
+&pci {
+ status = "okay";
+};
+
&pflash {
status = "okay";
status = "disabled";
};
+ pci: pci@fffe1000 {
+ compatible = "brcm,bcm6348-pci";
+ reg = <0xfffe1000 0x200>,
+ <0x08000000 0x10000>;
+ reg-names = "pci",
+ "pci-io";
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ bus-range = <0x00 0x01>;
+ ranges = <0x2000000 0 0x30000000 0x30000000 0 0x8000000>;
+ linux,pci-probe-only = <1>;
+
+ interrupt-parent = <&periph_intc>;
+ interrupts = <BCM6358_IRQ_MPI>;
+
+ resets = <&periph_rst BCM6358_RST_MPI>;
+ reset-names = "pci";
+
+ brcm,remap;
+
+ status = "disabled";
+ };
+
ehci: usb@fffe1300 {
compatible = "brcm,bcm6358-ehci", "generic-ehci";
reg = <0xfffe1300 0x100>;
status = "okay";
};
+&pcie {
+ status = "okay";
+};
+
&pinctrl {
pinctrl_leds: leds {
function = "led";
status = "disabled";
};
+ serdes_cntl: syscon@10001804 {
+ compatible = "syscon";
+ reg = <0x10001804 0x4>;
+ native-endian;
+ };
+
periph_pwr: power-controller@10001848 {
compatible = "brcm,bcm6362-power-controller";
reg = <0x10001848 0x4>;
reg = <1>;
};
};
+
+ pcie: pcie@10e40000 {
+ compatible = "brcm,bcm6328-pcie";
+ reg = <0x10e40000 0x10000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ bus-range = <0x00 0x01>;
+ ranges = <0x2000000 0 0x10f00000 0x10f00000 0 0x100000>;
+ linux,pci-probe-only = <1>;
+
+ interrupt-parent = <&periph_intc>;
+ interrupts = <BCM6362_IRQ_PCIE_RC>;
+
+ clocks = <&periph_clk BCM6362_CLK_PCIE>;
+ clock-names = "pcie";
+
+ resets = <&periph_rst BCM6362_RST_PCIE>,
+ <&periph_rst BCM6362_RST_PCIE_EXT>,
+ <&periph_rst BCM6362_RST_PCIE_CORE>;
+ reset-names = "pcie",
+ "pcie-ext",
+ "pcie-core";
+
+ power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_PCIE>;
+
+ brcm,serdes = <&serdes_cntl>;
+
+ status = "disabled";
+ };
};
};
status = "okay";
};
+&pci {
+ status = "okay";
+};
+
&pflash {
status = "okay";
status = "disabled";
};
+ pci: pci@10001000 {
+ compatible = "brcm,bcm6348-pci";
+ reg = <0x10001000 0x200>,
+ <0x08000000 0x10000>;
+ reg-names = "pci",
+ "pci-io";
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ bus-range = <0x00 0x01>;
+ ranges = <0x2000000 0 0x30000000 0x30000000 0 0x8000000>;
+ linux,pci-probe-only = <1>;
+
+ interrupt-parent = <&periph_intc>;
+ interrupts = <BCM6368_IRQ_MPI>;
+
+ resets = <&periph_rst BCM6368_RST_MPI>;
+ reset-names = "pci";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pci>;
+
+ brcm,remap;
+
+ status = "disabled";
+ };
+
ehci: usb@10001500 {
compatible = "brcm,bcm6368-ehci", "generic-ehci";
reg = <0x10001500 0x100>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <linux/pci.h>
+
+int bmips_pci_irq = -1;
+
+int pcibios_plat_dev_init(struct pci_dev *pci_dev)
+{
+ return PCIBIOS_SUCCESSFUL;
+}
+
+int pcibios_map_irq(const struct pci_dev *pci_dev, u8 slot, u8 pin)
+{
+ return bmips_pci_irq;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * BCM6348 PCI Controller Driver
+ *
+ * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ */
+
+#include <linux/clk.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/memblock.h>
+#include <linux/mm.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/reset.h>
+#include <linux/types.h>
+#include <linux/vmalloc.h>
+
+#include "../pci.h"
+
+#define CARDBUS_DUMMY_ID 0x6348
+#define CARDBUS_PCI_IDSEL 0x8
+#define FAKE_CB_BRIDGE_SLOT 0x1e
+
+#define BCMPCI_REG_TIMERS 0x40
+#define REG_TIMER_TRDY_SHIFT 0
+#define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
+#define REG_TIMER_RETRY_SHIFT 8
+#define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
+
+#define MPI_SP0_RANGE_REG 0x100
+#define MPI_SP0_REMAP_REG 0x104
+#define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
+#define MPI_SP1_RANGE_REG 0x10C
+#define MPI_SP1_REMAP_REG 0x110
+#define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
+
+#define MPI_L2PCFG_REG 0x11c
+#define MPI_L2PCFG_CFG_TYPE_SHIFT 0
+#define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
+#define MPI_L2PCFG_REG_SHIFT 2
+#define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
+#define MPI_L2PCFG_FUNC_SHIFT 8
+#define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
+#define MPI_L2PCFG_DEVNUM_SHIFT 11
+#define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
+#define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
+#define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
+
+#define MPI_L2PMEMRANGE1_REG 0x120
+#define MPI_L2PMEMBASE1_REG 0x124
+#define MPI_L2PMEMREMAP1_REG 0x128
+#define MPI_L2PMEMRANGE2_REG 0x12C
+#define MPI_L2PMEMBASE2_REG 0x130
+#define MPI_L2PMEMREMAP2_REG 0x134
+#define MPI_L2PIORANGE_REG 0x138
+#define MPI_L2PIOBASE_REG 0x13C
+#define MPI_L2PIOREMAP_REG 0x140
+#define MPI_L2P_BASE_MASK (0xffff8000)
+#define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
+#define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
+
+#define MPI_PCIMODESEL_REG 0x144
+#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
+#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
+#define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
+#define MPI_PCIMODESEL_PREFETCH_SHIFT 4
+#define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
+
+#define MPI_LOCBUSCTL_REG 0x14c
+#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
+#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
+
+#define MPI_LOCINT_REG 0x150
+#define MPI_LOCINT_MASK(x) (1 << (x + 16))
+#define MPI_LOCINT_STAT(x) (1 << (x))
+#define MPI_LOCINT_DIR_FAILED 6
+#define MPI_LOCINT_EXT_PCI_INT 7
+#define MPI_LOCINT_SERR 8
+#define MPI_LOCINT_CSERR 9
+
+#define MPI_PCICFGCTL_REG 0x178
+#define MPI_PCICFGCTL_CFGADDR_SHIFT 2
+#define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
+#define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
+
+#define MPI_PCICFGDATA_REG 0x17c
+
+#define PCMCIA_OFFSET 0x54
+
+#define PCMCIA_C1_REG 0x0
+#define PCMCIA_C1_CD1_MASK (1 << 0)
+#define PCMCIA_C1_CD2_MASK (1 << 1)
+#define PCMCIA_C1_VS1_MASK (1 << 2)
+#define PCMCIA_C1_VS2_MASK (1 << 3)
+#define PCMCIA_C1_VS1OE_MASK (1 << 6)
+#define PCMCIA_C1_VS2OE_MASK (1 << 7)
+#define PCMCIA_C1_CBIDSEL_SHIFT (8)
+#define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
+#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
+#define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
+#define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
+#define PCMCIA_C1_RESET_MASK (1 << 18)
+
+#ifdef CONFIG_CARDBUS
+struct bcm6348_cb {
+ u16 pci_command;
+ u8 cb_latency;
+ u8 subordinate_busn;
+ u8 cardbus_busn;
+ u8 pci_busn;
+ int bus_assigned;
+ u16 bridge_control;
+
+ u32 mem_base0;
+ u32 mem_limit0;
+ u32 mem_base1;
+ u32 mem_limit1;
+
+ u32 io_base0;
+ u32 io_limit0;
+ u32 io_base1;
+ u32 io_limit1;
+};
+#endif /* CONFIG_CARDBUS */
+
+struct bcm6348_pci {
+ void __iomem *pci;
+ void __iomem *pcmcia;
+ void __iomem *io;
+ int irq;
+ struct reset_control *reset;
+ bool remap;
+#ifdef CONFIG_CARDBUS
+ struct bcm6348_cb cb;
+ int cb_bus;
+#endif /* CONFIG_CARDBUS */
+};
+
+static struct bcm6348_pci bcm6348_pci;
+
+extern int bmips_pci_irq;
+
+static u32 bcm6348_int_cfg_readl(u32 reg)
+{
+ struct bcm6348_pci *priv = &bcm6348_pci;
+ u32 tmp;
+
+ tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
+ tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
+ __raw_writel(tmp, priv->pci + MPI_PCICFGCTL_REG);
+ iob();
+ return __raw_readl(priv->pci + MPI_PCICFGDATA_REG);
+}
+
+static void bcm6348_int_cfg_writel(u32 val, u32 reg)
+{
+ struct bcm6348_pci *priv = &bcm6348_pci;
+ u32 tmp;
+
+ tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
+ tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
+ __raw_writel(tmp, priv->pci + MPI_PCICFGCTL_REG);
+ __raw_writel(val, priv->pci + MPI_PCICFGDATA_REG);
+}
+
+/*
+ * swizzle 32bits data to return only the needed part
+ */
+static int postprocess_read(u32 data, int where, unsigned int size)
+{
+ u32 ret = 0;
+
+ switch (size) {
+ case 1:
+ ret = (data >> ((where & 3) << 3)) & 0xff;
+ break;
+ case 2:
+ ret = (data >> ((where & 3) << 3)) & 0xffff;
+ break;
+ case 4:
+ ret = data;
+ break;
+ }
+
+ return ret;
+}
+
+static int preprocess_write(u32 orig_data, u32 val, int where,
+ unsigned int size)
+{
+ u32 ret = 0;
+
+ switch (size) {
+ case 1:
+ ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+ break;
+ case 2:
+ ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+ break;
+ case 4:
+ ret = val;
+ break;
+ }
+
+ return ret;
+}
+
+static int bcm6348_setup_cfg_access(int type, unsigned int busn,
+ unsigned int devfn, int where)
+{
+ struct bcm6348_pci *priv = &bcm6348_pci;
+ unsigned int slot, func, reg;
+ u32 val;
+
+ slot = PCI_SLOT(devfn);
+ func = PCI_FUNC(devfn);
+ reg = where >> 2;
+
+ /* sanity check */
+ if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
+ return 1;
+
+ if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
+ return 1;
+
+ if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
+ return 1;
+
+ /* ok, setup config access */
+ val = (reg << MPI_L2PCFG_REG_SHIFT);
+ val |= (func << MPI_L2PCFG_FUNC_SHIFT);
+ val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
+ val |= MPI_L2PCFG_CFG_USEREG_MASK;
+ val |= MPI_L2PCFG_CFG_SEL_MASK;
+ /* type 0 cycle for local bus, type 1 cycle for anything else */
+ if (type != 0) {
+ /* FIXME: how to specify bus ??? */
+ val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
+ }
+ __raw_writel(val, priv->pci + MPI_L2PCFG_REG);
+
+ return 0;
+}
+
+
+static int bcm6348_do_cfg_read(int type, unsigned int busn,
+ unsigned int devfn, int where, int size,
+ u32 *val)
+{
+ struct bcm6348_pci *priv = &bcm6348_pci;
+ u32 data;
+
+ /* two phase cycle, first we write address, then read data at
+ * another location, caller already has a spinlock so no need
+ * to add one here */
+ if (bcm6348_setup_cfg_access(type, busn, devfn, where))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ iob();
+ data = le32_to_cpu(__raw_readl(priv->io));
+ /* restore IO space normal behaviour */
+ __raw_writel(0, priv->pci + MPI_L2PCFG_REG);
+
+ *val = postprocess_read(data, where, size);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int bcm6348_do_cfg_write(int type, unsigned int busn,
+ unsigned int devfn, int where, int size,
+ u32 val)
+{
+ struct bcm6348_pci *priv = &bcm6348_pci;
+ u32 data;
+
+ /* two phase cycle, first we write address, then write data to
+ * another location, caller already has a spinlock so no need
+ * to add one here */
+ if (bcm6348_setup_cfg_access(type, busn, devfn, where))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ iob();
+
+ data = le32_to_cpu(__raw_readl(priv->io));
+ data = preprocess_write(data, val, where, size);
+
+ __raw_writel(cpu_to_le32(data), priv->io);
+ wmb();
+ /* no way to know the access is done, we have to wait */
+ udelay(500);
+ /* restore IO space normal behaviour */
+ __raw_writel(0, priv->pci + MPI_L2PCFG_REG);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int bcm6348_pci_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ int type;
+
+ type = bus->parent ? 1 : 0;
+
+ if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ return bcm6348_do_cfg_read(type, bus->number, devfn,
+ where, size, val);
+}
+
+static int bcm6348_pci_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ int type;
+
+ type = bus->parent ? 1 : 0;
+
+ if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ return bcm6348_do_cfg_write(type, bus->number, devfn,
+ where, size, val);
+}
+
+static struct pci_ops bcm6348_pci_ops = {
+ .read = bcm6348_pci_read,
+ .write = bcm6348_pci_write,
+};
+
+static struct resource bcm6348_pci_io_resource = {
+ .name = "BCM6348 PCI IO space",
+ .flags = IORESOURCE_IO,
+};
+static struct resource bcm6348_pci_mem_resource;
+static struct resource bcm6348_pci_busn_resource;
+
+static struct pci_controller bcm6348_pci_controller = {
+ .pci_ops = &bcm6348_pci_ops,
+ .io_resource = &bcm6348_pci_io_resource,
+ .mem_resource = &bcm6348_pci_mem_resource,
+ .busn_resource = &bcm6348_pci_busn_resource,
+};
+
+#ifdef CONFIG_CARDBUS
+static int bcm6348_cb_bridge_read(int where, int size, u32 *val)
+{
+ struct bcm6348_cb *cb = &bcm6348_pci.cb;
+ unsigned int reg;
+ u32 data;
+
+ data = 0;
+ reg = where >> 2;
+ switch (reg) {
+ case (PCI_VENDOR_ID >> 2):
+ case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
+ /* create dummy vendor/device id from our cpu id */
+ data = (CARDBUS_DUMMY_ID << 16) | PCI_VENDOR_ID_BROADCOM;
+ break;
+
+ case (PCI_COMMAND >> 2):
+ data = (PCI_STATUS_DEVSEL_SLOW << 16);
+ data |= cb->pci_command;
+ break;
+
+ case (PCI_CLASS_REVISION >> 2):
+ data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
+ break;
+
+ case (PCI_CACHE_LINE_SIZE >> 2):
+ data = (PCI_HEADER_TYPE_CARDBUS << 16);
+ break;
+
+ case (PCI_INTERRUPT_LINE >> 2):
+ /* bridge control */
+ data = (cb->bridge_control << 16);
+ /* pin:intA line:0xff */
+ data |= (0x1 << 8) | 0xff;
+ break;
+
+ case (PCI_CB_PRIMARY_BUS >> 2):
+ data = (cb->cb_latency << 24);
+ data |= (cb->subordinate_busn << 16);
+ data |= (cb->cardbus_busn << 8);
+ data |= cb->pci_busn;
+ break;
+
+ case (PCI_CB_MEMORY_BASE_0 >> 2):
+ data = cb->mem_base0;
+ break;
+
+ case (PCI_CB_MEMORY_LIMIT_0 >> 2):
+ data = cb->mem_limit0;
+ break;
+
+ case (PCI_CB_MEMORY_BASE_1 >> 2):
+ data = cb->mem_base1;
+ break;
+
+ case (PCI_CB_MEMORY_LIMIT_1 >> 2):
+ data = cb->mem_limit1;
+ break;
+
+ case (PCI_CB_IO_BASE_0 >> 2):
+ /* | 1 for 32bits io support */
+ data = cb->io_base0 | 0x1;
+ break;
+
+ case (PCI_CB_IO_LIMIT_0 >> 2):
+ data = cb->io_limit0;
+ break;
+
+ case (PCI_CB_IO_BASE_1 >> 2):
+ /* | 1 for 32bits io support */
+ data = cb->io_base1 | 0x1;
+ break;
+
+ case (PCI_CB_IO_LIMIT_1 >> 2):
+ data = cb->io_limit1;
+ break;
+ }
+
+ *val = postprocess_read(data, where, size);
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/*
+ * emulate configuration write access on a cardbus bridge
+ */
+static int bcm6348_cb_bridge_write(int where, int size, u32 val)
+{
+ struct bcm6348_cb *cb = &bcm6348_pci.cb;
+ unsigned int reg;
+ u32 data, tmp;
+ int ret;
+
+ ret = bcm6348_cb_bridge_read((where & ~0x3), 4, &data);
+ if (ret != PCIBIOS_SUCCESSFUL)
+ return ret;
+
+ data = preprocess_write(data, val, where, size);
+
+ reg = where >> 2;
+ switch (reg) {
+ case (PCI_COMMAND >> 2):
+ cb->pci_command = (data & 0xffff);
+ break;
+
+ case (PCI_CB_PRIMARY_BUS >> 2):
+ cb->cb_latency = (data >> 24) & 0xff;
+ cb->subordinate_busn = (data >> 16) & 0xff;
+ cb->cardbus_busn = (data >> 8) & 0xff;
+ cb->pci_busn = data & 0xff;
+ if (cb->cardbus_busn)
+ cb->bus_assigned = 1;
+ break;
+
+ case (PCI_INTERRUPT_LINE >> 2):
+ tmp = (data >> 16) & 0xffff;
+ /* Disable memory prefetch support */
+ tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
+ tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
+ cb->bridge_control = tmp;
+ break;
+
+ case (PCI_CB_MEMORY_BASE_0 >> 2):
+ cb->mem_base0 = data;
+ break;
+
+ case (PCI_CB_MEMORY_LIMIT_0 >> 2):
+ cb->mem_limit0 = data;
+ break;
+
+ case (PCI_CB_MEMORY_BASE_1 >> 2):
+ cb->mem_base1 = data;
+ break;
+
+ case (PCI_CB_MEMORY_LIMIT_1 >> 2):
+ cb->mem_limit1 = data;
+ break;
+
+ case (PCI_CB_IO_BASE_0 >> 2):
+ cb->io_base0 = data;
+ break;
+
+ case (PCI_CB_IO_LIMIT_0 >> 2):
+ cb->io_limit0 = data;
+ break;
+
+ case (PCI_CB_IO_BASE_1 >> 2):
+ cb->io_base1 = data;
+ break;
+
+ case (PCI_CB_IO_LIMIT_1 >> 2):
+ cb->io_limit1 = data;
+ break;
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int bcm6348_cb_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct bcm6348_pci *priv = &bcm6348_pci;
+ struct bcm6348_cb *cb = &priv->cb;
+
+ /* Snoop access to slot 0x1e on root bus, we fake a cardbus
+ * bridge at this location */
+ if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
+ priv->cb_bus = bus->number;
+ return bcm6348_cb_bridge_read(where, size, val);
+ }
+
+ /* A configuration cycle for the device behind the cardbus
+ * bridge is actually done as a type 0 cycle on the primary
+ * bus. This means that only one device can be on the cardbus
+ * bus */
+ if (cb->bus_assigned &&
+ bus->number == cb->cardbus_busn &&
+ PCI_SLOT(devfn) == 0)
+ return bcm6348_do_cfg_read(0, 0,
+ PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
+ where, size, val);
+
+ return PCIBIOS_DEVICE_NOT_FOUND;
+}
+
+static int bcm6348_cb_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ struct bcm6348_pci *priv = &bcm6348_pci;
+ struct bcm6348_cb *cb = &priv->cb;
+
+ if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
+ priv->cb_bus = bus->number;
+ return bcm6348_cb_bridge_write(where, size, val);
+ }
+
+ if (cb->bus_assigned &&
+ bus->number == cb->cardbus_busn &&
+ PCI_SLOT(devfn) == 0)
+ return bcm6348_do_cfg_write(0, 0,
+ PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
+ where, size, val);
+
+ return PCIBIOS_DEVICE_NOT_FOUND;
+}
+
+static struct pci_ops bcm6348_cb_ops = {
+ .read = bcm6348_cb_read,
+ .write = bcm6348_cb_write,
+};
+
+/*
+ * only one IO window, so it cannot be shared by PCI and cardbus, use
+ * fixup to choose and detect unhandled configuration
+ */
+static void bcm6348_pci_fixup(struct pci_dev *dev)
+{
+ struct bcm6348_pci *priv = &bcm6348_pci;
+ struct bcm6348_cb *cb = &priv->cb;
+ static int io_window = -1;
+ int i, found, new_io_window;
+ u32 val;
+
+ /* look for any io resource */
+ found = 0;
+ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+ if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
+ found = 1;
+ break;
+ }
+ }
+
+ if (!found)
+ return;
+
+ /* skip our fake bus with only cardbus bridge on it */
+ if (dev->bus->number == priv->cb_bus)
+ return;
+
+ /* find on which bus the device is */
+ if (cb->bus_assigned &&
+ dev->bus->number == cb->cardbus_busn &&
+ PCI_SLOT(dev->devfn) == 0)
+ new_io_window = 1;
+ else
+ new_io_window = 0;
+
+ if (new_io_window == io_window)
+ return;
+
+ if (io_window != -1) {
+ pr_err("bcm63xx: both PCI and cardbus devices "
+ "need IO, which hardware cannot do\n");
+ return;
+ }
+
+ pr_info("bcm63xx: PCI IO window assigned to %s\n",
+ (new_io_window == 0) ? "PCI" : "cardbus");
+
+ val = __raw_readl(priv->pci + MPI_L2PIOREMAP_REG);
+ if (io_window)
+ val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
+ else
+ val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
+ __raw_writel(val, priv->pci + MPI_L2PIOREMAP_REG);
+
+ io_window = new_io_window;
+}
+DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm6348_pci_fixup);
+
+static struct resource bcm6348_cb_io_resource = {
+ .name = "bcm6348 CB IO space",
+ .flags = IORESOURCE_IO,
+};
+static struct resource bcm6348_cb_mem_resource;
+
+static struct pci_controller bcm6348_cb_controller = {
+ .pci_ops = &bcm6348_cb_ops,
+ .io_resource = &bcm6348_cb_io_resource,
+ .mem_resource = &bcm6348_cb_mem_resource,
+};
+#endif /* CONFIG_CARDBUS */
+
+static void bcm6348_pci_setup(struct bcm6348_pci *priv)
+{
+ u32 val;
+
+ /* Setup local bus to PCI access (PCI memory) */
+ val = bcm6348_pci_mem_resource.start & MPI_L2P_BASE_MASK;
+ __raw_writel(val, priv->pci + MPI_L2PMEMBASE1_REG);
+ __raw_writel(~(resource_size(&bcm6348_pci_mem_resource) - 1),
+ priv->pci + MPI_L2PMEMRANGE1_REG);
+ __raw_writel(val | MPI_L2PREMAP_ENABLED_MASK,
+ priv->pci + MPI_L2PMEMREMAP1_REG);
+
+ /* Set Cardbus IDSEL (type 0 cfg access on primary bus for
+ * this IDSEL will be done on Cardbus instead) */
+ val = __raw_readl(priv->pcmcia + PCMCIA_C1_REG);
+ val &= ~PCMCIA_C1_CBIDSEL_MASK;
+ val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
+ __raw_writel(val, priv->pcmcia + PCMCIA_C1_REG);
+
+#ifdef CONFIG_CARDBUS
+ /* setup local bus to PCI access (Cardbus memory) */
+ val = bcm6348_cb_mem_resource.start & MPI_L2P_BASE_MASK;
+ __raw_writel(val, priv->pci + MPI_L2PMEMBASE2_REG);
+ __raw_writel(~(resource_size(&bcm6348_cb_mem_resource) - 1),
+ priv->pci + MPI_L2PMEMRANGE2_REG);
+ val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
+ __raw_writel(val, priv->pci + MPI_L2PMEMREMAP2_REG);
+#else
+ /* disable second access windows */
+ __raw_writel(0, priv->pci + MPI_L2PMEMREMAP2_REG);
+#endif
+
+ /* setup local bus to PCI access (IO memory), we have only 1
+ * IO window for both PCI and cardbus, but it cannot handle
+ * both at the same time, assume standard PCI for now, if
+ * cardbus card has IO zone, PCI fixup will change window to
+ * cardbus */
+ val = bcm6348_pci_io_resource.start & MPI_L2P_BASE_MASK;
+ __raw_writel(val, priv->pci + MPI_L2PIOBASE_REG);
+ __raw_writel(~(resource_size(&bcm6348_pci_io_resource) - 1),
+ priv->pci + MPI_L2PIORANGE_REG);
+ __raw_writel(val | MPI_L2PREMAP_ENABLED_MASK,
+ priv->pci + MPI_L2PIOREMAP_REG);
+
+ /* Enable PCI related GPIO pins */
+ __raw_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK,
+ priv->pci + MPI_LOCBUSCTL_REG);
+
+ /* Setup PCI to local bus access, used by PCI device to target
+ * local RAM while bus mastering */
+ bcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
+ if (priv->remap)
+ val = MPI_SP0_REMAP_ENABLE_MASK;
+ else
+ val = 0;
+ __raw_writel(val, priv->pci + MPI_SP0_REMAP_REG);
+
+ bcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_4);
+ __raw_writel(0, priv->pci + MPI_SP1_REMAP_REG);
+
+ /* Setup sp0 range to local RAM size */
+ __raw_writel(~(memblock_phys_mem_size() - 1),
+ priv->pci + MPI_SP0_RANGE_REG);
+ __raw_writel(0, priv->pci + MPI_SP1_RANGE_REG);
+
+ /* Change host bridge retry counter to infinite number of
+ * retries, needed for some broadcom wifi cards with Silicon
+ * Backplane bus where access to srom seems very slow */
+ val = bcm6348_int_cfg_readl(BCMPCI_REG_TIMERS);
+ val &= ~REG_TIMER_RETRY_MASK;
+ bcm6348_int_cfg_writel(val, BCMPCI_REG_TIMERS);
+
+ /* EEnable memory decoder and bus mastering */
+ val = bcm6348_int_cfg_readl(PCI_COMMAND);
+ val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ bcm6348_int_cfg_writel(val, PCI_COMMAND);
+
+ /* Enable read prefetching & disable byte swapping for bus
+ * mastering transfers */
+ val = __raw_readl(priv->pci + MPI_PCIMODESEL_REG);
+ val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
+ val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
+ val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
+ val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
+ __raw_writel(val, priv->pci + MPI_PCIMODESEL_REG);
+
+ /* Enable pci interrupt */
+ val = __raw_readl(priv->pci + MPI_LOCINT_REG);
+ val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
+ __raw_writel(val, priv->pci + MPI_LOCINT_REG);
+}
+
+static int bcm6348_pci_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct bcm6348_pci *priv = &bcm6348_pci;
+ struct resource *res;
+
+ of_pci_check_probe_only();
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pci");
+ priv->pci = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->pci))
+ return PTR_ERR(priv->pci);
+
+ priv->pcmcia = priv->pci + PCMCIA_OFFSET;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pci-io");
+ if (!res)
+ return -EINVAL;
+#ifdef CONFIG_CARDBUS
+ bcm6348_pci_io_resource.start = res->start;
+ bcm6348_pci_io_resource.end = res->end - (resource_size(res) >> 1);
+ bcm6348_cb_io_resource.start = res->start + (resource_size(res) >> 1);
+ bcm6348_cb_io_resource.end = res->end;
+#else
+ bcm6348_pci_io_resource.start = res->start;
+ bcm6348_pci_io_resource.end = res->end;
+#endif
+
+ priv->irq = platform_get_irq(pdev, 0);
+ if (!priv->irq)
+ return -ENODEV;
+
+ bmips_pci_irq = priv->irq;
+
+ priv->reset = devm_reset_control_get(dev, "pci");
+ if (IS_ERR(priv->reset))
+ return PTR_ERR(priv->reset);
+
+ priv->remap = of_property_read_bool(np, "brcm,remap");
+
+ reset_control_reset(priv->reset);
+
+ pci_load_of_ranges(&bcm6348_pci_controller, np);
+ if (!bcm6348_pci_mem_resource.start)
+ return -EINVAL;
+
+ of_pci_parse_bus_range(np, &bcm6348_pci_busn_resource);
+
+ /*
+ * Configuration accesses are done through IO space, remap 4
+ * first bytes to access it from CPU.
+ *
+ * This means that no IO access from CPU should happen while
+ * we do a configuration cycle, but there's no way we can add
+ * a spinlock for each io access, so this is currently kind of
+ * broken on SMP.
+ */
+ priv->io = ioremap(bcm6348_pci_io_resource.start, sizeof(u32));
+ if (!priv->io)
+ return -ENOMEM;
+
+ bcm6348_pci_setup(priv);
+
+ register_pci_controller(&bcm6348_pci_controller);
+
+#ifdef CONFIG_CARDBUS
+ priv->cb_bus = -1;
+ register_pci_controller(&bcm6348_cb_controller);
+#endif /* CONFIG_CARDBUS */
+
+ /* Mark memory space used for IO mapping as reserved */
+ request_mem_region(bcm6348_pci_io_resource.start,
+ resource_size(&bcm6348_pci_io_resource),
+ "BCM6348 PCI IO space");
+
+ return 0;
+}
+
+static const struct of_device_id bcm6348_pci_of_match[] = {
+ { .compatible = "brcm,bcm6348-pci", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver bcm6348_pci_driver = {
+ .probe = bcm6348_pci_probe,
+ .driver = {
+ .name = "bcm6348-pci",
+ .of_match_table = bcm6348_pci_of_match,
+ },
+};
+
+int __init bcm6348_pci_init(void)
+{
+ int ret = platform_driver_register(&bcm6348_pci_driver);
+ if (ret)
+ pr_err("pci-bcm6348: Error registering platform driver!\n");
+ return ret;
+}
+late_initcall_sync(bcm6348_pci_init);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * BCM6318 PCIe Controller Driver
+ *
+ * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ */
+
+#include <linux/clk.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/of_gpio.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/reset.h>
+#include <linux/types.h>
+#include <linux/vmalloc.h>
+
+#include "../pci.h"
+
+#define PCIE_BUS_BRIDGE 0
+#define PCIE_BUS_DEVICE 1
+
+#define PCIE_SPECIFIC_REG 0x188
+#define SPECIFIC_ENDIAN_MODE_BAR1_SHIFT 0
+#define SPECIFIC_ENDIAN_MODE_BAR1_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
+#define SPECIFIC_ENDIAN_MODE_BAR2_SHIFT 2
+#define SPECIFIC_ENDIAN_MODE_BAR2_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
+#define SPECIFIC_ENDIAN_MODE_BAR3_SHIFT 4
+#define SPECIFIC_ENDIAN_MODE_BAR3_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
+#define SPECIFIC_ENDIAN_MODE_WORD_ALIGN 0
+#define SPECIFIC_ENDIAN_MODE_HALFWORD_ALIGN 1
+#define SPECIFIC_ENDIAN_MODE_BYTE_ALIGN 2
+
+#define PCIE_CONFIG2_REG 0x408
+#define CONFIG2_BAR1_SIZE_EN 1
+#define CONFIG2_BAR1_SIZE_MASK 0xf
+
+#define PCIE_IDVAL3_REG 0x43c
+#define IDVAL3_CLASS_CODE_MASK 0xffffff
+#define IDVAL3_SUBCLASS_SHIFT 8
+#define IDVAL3_CLASS_SHIFT 16
+
+#define PCIE_DLSTATUS_REG 0x1048
+#define DLSTATUS_PHYLINKUP (1 << 13)
+
+#define PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG 0x400c
+#define C2P_MEM_WIN_ENDIAN_MODE_MASK 0x3
+#define C2P_MEM_WIN_ENDIAN_NO_SWAP 0
+#define C2P_MEM_WIN_ENDIAN_HALF_WORD_SWAP 1
+#define C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP 2
+#define C2P_MEM_WIN_BASE_ADDR_SHIFT 20
+#define C2P_MEM_WIN_BASE_ADDR_MASK (0xfff << C2P_MEM_WIN_BASE_ADDR_SHIFT)
+
+#define PCIE_RC_BAR1_CONFIG_LO_REG 0x402c
+#define RC_BAR_CFG_LO_SIZE_256MB 0xd
+#define RC_BAR_CFG_LO_MATCH_ADDR_SHIFT 20
+#define RC_BAR_CFG_LO_MATCH_ADDR_MASK (0xfff << RC_BAR_CFG_LO_MATCH_ADDR_SHIFT)
+
+#define PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG 0x4070
+#define C2P_BASELIMIT_LIMIT_SHIFT 20
+#define C2P_BASELIMIT_LIMIT_MASK (0xfff << C2P_BASELIMIT_LIMIT_SHIFT)
+#define C2P_BASELIMIT_BASE_SHIFT 4
+#define C2P_BASELIMIT_BASE_MASK (0xfff << C2P_BASELIMIT_BASE_SHIFT)
+
+#define PCIE_UBUS_BAR1_CFG_REMAP_REG 0x4088
+#define BAR1_CFG_REMAP_OFFSET_SHIFT 20
+#define BAR1_CFG_REMAP_OFFSET_MASK (0xfff << BAR1_CFG_REMAP_OFFSET_SHIFT)
+#define BAR1_CFG_REMAP_ACCESS_EN 1
+
+#define PCIE_HARD_DEBUG_REG 0x4204
+#define HARD_DEBUG_SERDES_IDDQ (1 << 23)
+
+#define PCIE_CPU_INT1_MASK_CLEAR_REG 0x830c
+#define CPU_INT_PCIE_ERR_ATTN_CPU (1 << 0)
+#define CPU_INT_PCIE_INTA (1 << 1)
+#define CPU_INT_PCIE_INTB (1 << 2)
+#define CPU_INT_PCIE_INTC (1 << 3)
+#define CPU_INT_PCIE_INTD (1 << 4)
+#define CPU_INT_PCIE_INTR (1 << 5)
+#define CPU_INT_PCIE_NMI (1 << 6)
+#define CPU_INT_PCIE_UBUS (1 << 7)
+#define CPU_INT_IPI (1 << 8)
+
+#define PCIE_EXT_CFG_INDEX_REG 0x8400
+#define EXT_CFG_FUNC_NUM_SHIFT 12
+#define EXT_CFG_FUNC_NUM_MASK (0x7 << EXT_CFG_FUNC_NUM_SHIFT)
+#define EXT_CFG_DEV_NUM_SHIFT 15
+#define EXT_CFG_DEV_NUM_MASK (0xf << EXT_CFG_DEV_NUM_SHIFT)
+#define EXT_CFG_BUS_NUM_SHIFT 20
+#define EXT_CFG_BUS_NUM_MASK (0xff << EXT_CFG_BUS_NUM_SHIFT)
+
+#define PCIE_DEVICE_OFFSET 0x9000
+
+struct bcm6318_pcie {
+ void __iomem *base;
+ int irq;
+ struct clk *clk;
+ struct clk *clk25;
+ struct clk *clk_ubus;
+ struct reset_control *reset;
+ struct reset_control *reset_ext;
+ struct reset_control *reset_core;
+ struct reset_control *reset_hard;
+};
+
+static struct bcm6318_pcie bcm6318_pcie;
+
+extern int bmips_pci_irq;
+
+/*
+ * swizzle 32bits data to return only the needed part
+ */
+static int postprocess_read(u32 data, int where, unsigned int size)
+{
+ u32 ret = 0;
+
+ switch (size) {
+ case 1:
+ ret = (data >> ((where & 3) << 3)) & 0xff;
+ break;
+ case 2:
+ ret = (data >> ((where & 3) << 3)) & 0xffff;
+ break;
+ case 4:
+ ret = data;
+ break;
+ }
+
+ return ret;
+}
+
+static int preprocess_write(u32 orig_data, u32 val, int where,
+ unsigned int size)
+{
+ u32 ret = 0;
+
+ switch (size) {
+ case 1:
+ ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+ break;
+ case 2:
+ ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+ break;
+ case 4:
+ ret = val;
+ break;
+ }
+
+ return ret;
+}
+
+static int bcm6318_pcie_can_access(struct pci_bus *bus, int devfn)
+{
+ struct bcm6318_pcie *priv = &bcm6318_pcie;
+
+ switch (bus->number) {
+ case PCIE_BUS_BRIDGE:
+ return PCI_SLOT(devfn) == 0;
+ case PCIE_BUS_DEVICE:
+ if (PCI_SLOT(devfn) == 0)
+ return __raw_readl(priv->base + PCIE_DLSTATUS_REG)
+ & DLSTATUS_PHYLINKUP;
+ /* else, fall through */
+ default:
+ return false;
+ }
+}
+
+static int bcm6318_pcie_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct bcm6318_pcie *priv = &bcm6318_pcie;
+ u32 data;
+ u32 reg = where & ~3;
+
+ if (!bcm6318_pcie_can_access(bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ if (bus->number == PCIE_BUS_DEVICE)
+ reg += PCIE_DEVICE_OFFSET;
+
+ data = __raw_readl(priv->base + reg);
+ *val = postprocess_read(data, where, size);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int bcm6318_pcie_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ struct bcm6318_pcie *priv = &bcm6318_pcie;
+ u32 data;
+ u32 reg = where & ~3;
+
+ if (!bcm6318_pcie_can_access(bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ if (bus->number == PCIE_BUS_DEVICE)
+ reg += PCIE_DEVICE_OFFSET;
+
+ data = __raw_readl(priv->base + reg);
+ data = preprocess_write(data, val, where, size);
+ __raw_writel(data, priv->base + reg);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops bcm6318_pcie_ops = {
+ .read = bcm6318_pcie_read,
+ .write = bcm6318_pcie_write,
+};
+
+static struct resource bcm6318_pcie_io_resource;
+static struct resource bcm6318_pcie_mem_resource;
+static struct resource bcm6318_pcie_busn_resource;
+
+static struct pci_controller bcm6318_pcie_controller = {
+ .pci_ops = &bcm6318_pcie_ops,
+ .io_resource = &bcm6318_pcie_io_resource,
+ .mem_resource = &bcm6318_pcie_mem_resource,
+ .busn_resource = &bcm6318_pcie_busn_resource,
+};
+
+static void bcm6318_pcie_reset(struct bcm6318_pcie *priv)
+{
+ u32 val;
+
+ reset_control_deassert(priv->reset_hard);
+
+ reset_control_assert(priv->reset);
+ reset_control_assert(priv->reset_core);
+ reset_control_assert(priv->reset_ext);
+ mdelay(10);
+
+ reset_control_deassert(priv->reset_ext);
+ mdelay(10);
+
+ reset_control_deassert(priv->reset);
+ mdelay(10);
+
+ val = __raw_readl(priv->base + PCIE_HARD_DEBUG_REG);
+ val &= ~HARD_DEBUG_SERDES_IDDQ;
+ __raw_writel(val, priv->base + PCIE_HARD_DEBUG_REG);
+ mdelay(10);
+
+ reset_control_deassert(priv->reset_core);
+ mdelay(200);
+}
+
+static void bcm6318_pcie_setup(struct bcm6318_pcie *priv)
+{
+ u32 val;
+
+ __raw_writel(CPU_INT_PCIE_INTA | CPU_INT_PCIE_INTB |
+ CPU_INT_PCIE_INTC | CPU_INT_PCIE_INTD,
+ priv->base + PCIE_CPU_INT1_MASK_CLEAR_REG);
+
+ val = bcm6318_pcie_mem_resource.end & C2P_BASELIMIT_LIMIT_MASK;
+ val |= (bcm6318_pcie_mem_resource.start >> C2P_BASELIMIT_LIMIT_SHIFT)
+ << C2P_BASELIMIT_BASE_SHIFT;
+ __raw_writel(val, priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG);
+
+ /* setup class code as bridge */
+ val = __raw_readl(priv->base + PCIE_IDVAL3_REG);
+ val &= ~IDVAL3_CLASS_CODE_MASK;
+ val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
+ __raw_writel(val, priv->base + PCIE_IDVAL3_REG);
+
+ /* disable bar1 size */
+ val = __raw_readl(priv->base + PCIE_CONFIG2_REG);
+ val &= ~CONFIG2_BAR1_SIZE_MASK;
+ __raw_writel(val, priv->base + PCIE_CONFIG2_REG);
+
+ /* set bar0 to little endian */
+ val = __raw_readl(priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);
+ val |= bcm6318_pcie_mem_resource.start & C2P_MEM_WIN_BASE_ADDR_MASK;
+ val |= C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP;
+ __raw_writel(val, priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);
+
+ __raw_writel(SPECIFIC_ENDIAN_MODE_BYTE_ALIGN,
+ priv->base + PCIE_SPECIFIC_REG);
+
+ __raw_writel(RC_BAR_CFG_LO_SIZE_256MB,
+ priv->base + PCIE_RC_BAR1_CONFIG_LO_REG);
+
+ __raw_writel(BAR1_CFG_REMAP_ACCESS_EN,
+ priv->base + PCIE_UBUS_BAR1_CFG_REMAP_REG);
+
+ __raw_writel(PCIE_BUS_DEVICE << EXT_CFG_BUS_NUM_SHIFT,
+ priv->base + PCIE_EXT_CFG_INDEX_REG);
+}
+
+static int bcm6318_pcie_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct bcm6318_pcie *priv = &bcm6318_pcie;
+ struct resource *res;
+ int ret;
+
+ of_pci_check_probe_only();
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->irq = platform_get_irq(pdev, 0);
+ if (!priv->irq)
+ return -ENODEV;
+
+ bmips_pci_irq = priv->irq;
+
+ priv->reset = devm_reset_control_get(dev, "pcie");
+ if (IS_ERR(priv->reset))
+ return PTR_ERR(priv->reset);
+
+ priv->reset_ext = devm_reset_control_get(dev, "pcie-ext");
+ if (IS_ERR(priv->reset_ext))
+ return PTR_ERR(priv->reset_ext);
+
+ priv->reset_core = devm_reset_control_get(dev, "pcie-core");
+ if (IS_ERR(priv->reset_core))
+ return PTR_ERR(priv->reset_core);
+
+ priv->reset_hard = devm_reset_control_get(dev, "pcie-hard");
+ if (IS_ERR(priv->reset_hard))
+ return PTR_ERR(priv->reset_hard);
+
+ priv->clk = devm_clk_get(dev, "pcie");
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+
+ priv->clk25 = devm_clk_get(dev, "pcie25");
+ if (IS_ERR(priv->clk25))
+ return PTR_ERR(priv->clk25);
+
+ priv->clk_ubus = devm_clk_get(dev, "pcie-ubus");
+ if (IS_ERR(priv->clk_ubus))
+ return PTR_ERR(priv->clk_ubus);
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret) {
+ dev_err(dev, "could not enable clock\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(priv->clk25);
+ if (ret) {
+ dev_err(dev, "could not enable clock\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(priv->clk_ubus);
+ if (ret) {
+ dev_err(dev, "could not enable clock\n");
+ return ret;
+ }
+
+ pci_load_of_ranges(&bcm6318_pcie_controller, np);
+ if (!bcm6318_pcie_mem_resource.start)
+ return -EINVAL;
+
+ of_pci_parse_bus_range(np, &bcm6318_pcie_busn_resource);
+
+ bcm6318_pcie_reset(priv);
+ bcm6318_pcie_setup(priv);
+
+ register_pci_controller(&bcm6318_pcie_controller);
+
+ return 0;
+}
+
+static const struct of_device_id bcm6318_pcie_of_match[] = {
+ { .compatible = "brcm,bcm6318-pcie", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver bcm6318_pcie_driver = {
+ .probe = bcm6318_pcie_probe,
+ .driver = {
+ .name = "bcm6318-pcie",
+ .of_match_table = bcm6318_pcie_of_match,
+ },
+};
+
+int __init bcm6318_pcie_init(void)
+{
+ int ret = platform_driver_register(&bcm6318_pcie_driver);
+ if (ret)
+ pr_err("pci-bcm6318: Error registering platform driver!\n");
+ return ret;
+}
+late_initcall_sync(bcm6318_pcie_init);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * BCM6328 PCIe Controller Driver
+ *
+ * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ */
+
+#include <linux/clk.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mm.h>
+#include <linux/of_gpio.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+#include <linux/vmalloc.h>
+
+#include "../pci.h"
+
+#define SERDES_PCIE_EXD_EN BIT(15)
+#define SERDES_PCIE_EN BIT(0)
+
+#define PCIE_BUS_BRIDGE 0
+#define PCIE_BUS_DEVICE 1
+
+#define PCIE_CONFIG2_REG 0x408
+#define CONFIG2_BAR1_SIZE_EN 1
+#define CONFIG2_BAR1_SIZE_MASK 0xf
+
+#define PCIE_IDVAL3_REG 0x43c
+#define IDVAL3_CLASS_CODE_MASK 0xffffff
+#define IDVAL3_SUBCLASS_SHIFT 8
+#define IDVAL3_CLASS_SHIFT 16
+
+#define PCIE_DLSTATUS_REG 0x1048
+#define DLSTATUS_PHYLINKUP (1 << 13)
+
+#define PCIE_BRIDGE_OPT1_REG 0x2820
+#define OPT1_RD_BE_OPT_EN (1 << 7)
+#define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
+#define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
+#define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
+
+#define PCIE_BRIDGE_OPT2_REG 0x2824
+#define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
+#define OPT2_TX_CREDIT_CHK_EN (1 << 4)
+#define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
+#define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
+#define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
+
+#define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
+#define BASEMASK_REMAP_EN (1 << 0)
+#define BASEMASK_SWAP_EN (1 << 1)
+#define BASEMASK_MASK_SHIFT 4
+#define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
+#define BASEMASK_BASE_SHIFT 20
+#define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
+
+#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
+#define REBASE_ADDR_BASE_SHIFT 20
+#define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
+
+#define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
+#define PCIE_RC_INT_A (1 << 0)
+#define PCIE_RC_INT_B (1 << 1)
+#define PCIE_RC_INT_C (1 << 2)
+#define PCIE_RC_INT_D (1 << 3)
+
+#define PCIE_DEVICE_OFFSET 0x8000
+
+struct bcm6328_pcie {
+ void __iomem *base;
+ int irq;
+ struct regmap *serdes;
+ struct device **pm;
+ struct device_link **link_pm;
+ unsigned int num_pms;
+ struct clk *clk;
+ struct reset_control *reset;
+ struct reset_control *reset_ext;
+ struct reset_control *reset_core;
+ struct reset_control *reset_hard;
+};
+
+static struct bcm6328_pcie bcm6328_pcie;
+
+extern int bmips_pci_irq;
+
+/*
+ * swizzle 32bits data to return only the needed part
+ */
+static int postprocess_read(u32 data, int where, unsigned int size)
+{
+ u32 ret = 0;
+
+ switch (size) {
+ case 1:
+ ret = (data >> ((where & 3) << 3)) & 0xff;
+ break;
+ case 2:
+ ret = (data >> ((where & 3) << 3)) & 0xffff;
+ break;
+ case 4:
+ ret = data;
+ break;
+ }
+
+ return ret;
+}
+
+static int preprocess_write(u32 orig_data, u32 val, int where,
+ unsigned int size)
+{
+ u32 ret = 0;
+
+ switch (size) {
+ case 1:
+ ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+ break;
+ case 2:
+ ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+ break;
+ case 4:
+ ret = val;
+ break;
+ }
+
+ return ret;
+}
+
+static int bcm6328_pcie_can_access(struct pci_bus *bus, int devfn)
+{
+ struct bcm6328_pcie *priv = &bcm6328_pcie;
+
+ switch (bus->number) {
+ case PCIE_BUS_BRIDGE:
+ return PCI_SLOT(devfn) == 0;
+ case PCIE_BUS_DEVICE:
+ if (PCI_SLOT(devfn) == 0)
+ return __raw_readl(priv->base + PCIE_DLSTATUS_REG)
+ & DLSTATUS_PHYLINKUP;
+ /* else, fall through */
+ default:
+ return false;
+ }
+}
+
+static int bcm6328_pcie_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct bcm6328_pcie *priv = &bcm6328_pcie;
+ u32 data;
+ u32 reg = where & ~3;
+
+ if (!bcm6328_pcie_can_access(bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ if (bus->number == PCIE_BUS_DEVICE)
+ reg += PCIE_DEVICE_OFFSET;
+
+ data = __raw_readl(priv->base + reg);
+ *val = postprocess_read(data, where, size);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int bcm6328_pcie_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ struct bcm6328_pcie *priv = &bcm6328_pcie;
+ u32 data;
+ u32 reg = where & ~3;
+
+ if (!bcm6328_pcie_can_access(bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ if (bus->number == PCIE_BUS_DEVICE)
+ reg += PCIE_DEVICE_OFFSET;
+
+ data = __raw_readl(priv->base + reg);
+ data = preprocess_write(data, val, where, size);
+ __raw_writel(data, priv->base + reg);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops bcm6328_pcie_ops = {
+ .read = bcm6328_pcie_read,
+ .write = bcm6328_pcie_write,
+};
+
+static struct resource bcm6328_pcie_io_resource;
+static struct resource bcm6328_pcie_mem_resource;
+static struct resource bcm6328_pcie_busn_resource;
+
+static struct pci_controller bcm6328_pcie_controller = {
+ .pci_ops = &bcm6328_pcie_ops,
+ .io_resource = &bcm6328_pcie_io_resource,
+ .mem_resource = &bcm6328_pcie_mem_resource,
+ .busn_resource = &bcm6328_pcie_busn_resource,
+};
+
+static void bcm6328_pcie_reset(struct bcm6328_pcie *priv)
+{
+ regmap_write_bits(priv->serdes, 0,
+ SERDES_PCIE_EXD_EN | SERDES_PCIE_EN,
+ SERDES_PCIE_EXD_EN | SERDES_PCIE_EN);
+
+ reset_control_assert(priv->reset);
+ reset_control_assert(priv->reset_core);
+ reset_control_assert(priv->reset_ext);
+ if (priv->reset_hard) {
+ reset_control_assert(priv->reset_hard);
+ mdelay(10);
+ reset_control_deassert(priv->reset_hard);
+ }
+ mdelay(10);
+
+ reset_control_deassert(priv->reset_core);
+ reset_control_deassert(priv->reset);
+ mdelay(10);
+
+ reset_control_deassert(priv->reset_ext);
+ mdelay(200);
+}
+
+static void bcm6328_pcie_setup(struct bcm6328_pcie *priv)
+{
+ u32 val;
+
+ val = __raw_readl(priv->base + PCIE_BRIDGE_OPT1_REG);
+ val |= OPT1_RD_BE_OPT_EN;
+ val |= OPT1_RD_REPLY_BE_FIX_EN;
+ val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
+ val |= OPT1_L1_INT_STATUS_MASK_POL;
+ __raw_writel(val, priv->base + PCIE_BRIDGE_OPT1_REG);
+
+ val = __raw_readl(priv->base + PCIE_BRIDGE_RC_INT_MASK_REG);
+ val |= PCIE_RC_INT_A;
+ val |= PCIE_RC_INT_B;
+ val |= PCIE_RC_INT_C;
+ val |= PCIE_RC_INT_D;
+ __raw_writel(val, priv->base + PCIE_BRIDGE_RC_INT_MASK_REG);
+
+ val = __raw_readl(priv->base + PCIE_BRIDGE_OPT2_REG);
+ /* enable credit checking and error checking */
+ val |= OPT2_TX_CREDIT_CHK_EN;
+ val |= OPT2_UBUS_UR_DECODE_DIS;
+ /* set device bus/func for the pcie device */
+ val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
+ val |= OPT2_CFG_TYPE1_BD_SEL;
+ __raw_writel(val, priv->base + PCIE_BRIDGE_OPT2_REG);
+
+ /* setup class code as bridge */
+ val = __raw_readl(priv->base + PCIE_IDVAL3_REG);
+ val &= ~IDVAL3_CLASS_CODE_MASK;
+ val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
+ __raw_writel(val, priv->base + PCIE_IDVAL3_REG);
+
+ /* disable bar1 size */
+ val = __raw_readl(priv->base + PCIE_CONFIG2_REG);
+ val &= ~CONFIG2_BAR1_SIZE_MASK;
+ __raw_writel(val, priv->base + PCIE_CONFIG2_REG);
+
+ /* set bar0 to little endian */
+ val = (bcm6328_pcie_mem_resource.start >> 20)
+ << BASEMASK_BASE_SHIFT;
+ val |= (bcm6328_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;
+ val |= BASEMASK_REMAP_EN;
+ __raw_writel(val, priv->base + PCIE_BRIDGE_BAR0_BASEMASK_REG);
+
+ val = (bcm6328_pcie_mem_resource.start >> 20)
+ << REBASE_ADDR_BASE_SHIFT;
+ __raw_writel(val, priv->base + PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
+}
+
+static int bcm6328_pcie_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct bcm6328_pcie *priv = &bcm6328_pcie;
+ struct resource *res;
+ unsigned int i;
+ int ret;
+
+ pm_runtime_enable(dev);
+ pm_runtime_no_callbacks(dev);
+
+ priv->num_pms = of_count_phandle_with_args(np, "power-domains",
+ "#power-domain-cells");
+ if (priv->num_pms > 1) {
+ priv->pm = devm_kcalloc(dev, priv->num_pms,
+ sizeof(struct device *), GFP_KERNEL);
+ if (!priv->pm)
+ return -ENOMEM;
+
+ priv->link_pm = devm_kcalloc(dev, priv->num_pms,
+ sizeof(struct device_link *),
+ GFP_KERNEL);
+ if (!priv->link_pm)
+ return -ENOMEM;
+
+ for (i = 0; i < priv->num_pms; i++) {
+ priv->pm[i] = genpd_dev_pm_attach_by_id(dev, i);
+ if (IS_ERR(priv->pm[i])) {
+ dev_err(dev, "error getting pm %d\n", i);
+ return -EINVAL;
+ }
+
+ priv->link_pm[i] = device_link_add(dev, priv->pm[i],
+ DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |
+ DL_FLAG_RPM_ACTIVE);
+ }
+ }
+
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0) {
+ pm_runtime_disable(dev);
+ dev_info(dev, "PM prober defer: ret=%d\n", ret);
+ return -EPROBE_DEFER;
+ }
+
+ of_pci_check_probe_only();
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->irq = platform_get_irq(pdev, 0);
+ if (!priv->irq)
+ return -ENODEV;
+
+ bmips_pci_irq = priv->irq;
+
+ priv->serdes = syscon_regmap_lookup_by_phandle(np, "brcm,serdes");
+ if (IS_ERR(priv->serdes))
+ return PTR_ERR(priv->serdes);
+
+ priv->reset = devm_reset_control_get(dev, "pcie");
+ if (IS_ERR(priv->reset))
+ return PTR_ERR(priv->reset);
+
+ priv->reset_ext = devm_reset_control_get(dev, "pcie-ext");
+ if (IS_ERR(priv->reset_ext))
+ return PTR_ERR(priv->reset_ext);
+
+ priv->reset_core = devm_reset_control_get(dev, "pcie-core");
+ if (IS_ERR(priv->reset_core))
+ return PTR_ERR(priv->reset_core);
+
+ priv->reset_hard = devm_reset_control_get_optional(dev, "pcie-hard");
+ if (IS_ERR(priv->reset_hard))
+ return PTR_ERR(priv->reset_hard);
+
+ priv->clk = devm_clk_get(dev, "pcie");
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret) {
+ dev_err(dev, "could not enable clock\n");
+ return ret;
+ }
+
+ pci_load_of_ranges(&bcm6328_pcie_controller, np);
+ if (!bcm6328_pcie_mem_resource.start)
+ return -EINVAL;
+
+ of_pci_parse_bus_range(np, &bcm6328_pcie_busn_resource);
+
+ bcm6328_pcie_reset(priv);
+ bcm6328_pcie_setup(priv);
+
+ register_pci_controller(&bcm6328_pcie_controller);
+
+ return 0;
+}
+
+static const struct of_device_id bcm6328_pcie_of_match[] = {
+ { .compatible = "brcm,bcm6328-pcie", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver bcm6328_pcie_driver = {
+ .probe = bcm6328_pcie_probe,
+ .driver = {
+ .name = "bcm6328-pcie",
+ .of_match_table = bcm6328_pcie_of_match,
+ },
+};
+
+int __init bcm6328_pcie_init(void)
+{
+ int ret = platform_driver_register(&bcm6328_pcie_driver);
+ if (ret)
+ pr_err("pci-bcm6328: Error registering platform driver!\n");
+ return ret;
+}
+late_initcall_sync(bcm6328_pcie_init);
--- /dev/null
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -262,6 +262,7 @@ config BMIPS_GENERIC
+ select BCM7038_L1_IRQ
+ select BCM7120_L2_IRQ
+ select BRCMSTB_L2_IRQ
++ select HAVE_PCI
+ select IRQ_MIPS_CPU
+ select DMA_NONCOHERENT
+ select SYS_SUPPORTS_32BIT_KERNEL
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -28,6 +28,7 @@ obj-$(CONFIG_PCI_XTALK_BRIDGE) += pci-xt
+ # These are still pretty much in the old state, watch, go blind.
+ #
+ obj-$(CONFIG_ATH79) += fixup-ath79.o
++obj-$(CONFIG_BMIPS_GENERIC) += fixup-bmips.o
+ obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
+ obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
+ obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
--- /dev/null
+--- a/drivers/pci/controller/Kconfig
++++ b/drivers/pci/controller/Kconfig
+@@ -3,6 +3,11 @@
+ menu "PCI controller drivers"
+ depends on PCI
+
++config PCIE_BCM6328
++ bool "BCM6328 PCIe controller"
++ depends on BMIPS_GENERIC || COMPILE_TEST
++ depends on OF
++
+ config PCI_MVEBU
+ bool "Marvell EBU PCIe controller"
+ depends on ARCH_MVEBU || ARCH_DOVE || COMPILE_TEST
+--- a/drivers/pci/controller/Makefile
++++ b/drivers/pci/controller/Makefile
+@@ -1,4 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_PCIE_BCM6328) += pcie-bcm6328.o
+ obj-$(CONFIG_PCIE_CADENCE) += cadence/
+ obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o
+ obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o
--- /dev/null
+--- a/drivers/pci/controller/Kconfig
++++ b/drivers/pci/controller/Kconfig
+@@ -3,6 +3,11 @@
+ menu "PCI controller drivers"
+ depends on PCI
+
++config PCIE_BCM6318
++ bool "BCM6318 PCIe controller"
++ depends on BMIPS_GENERIC || COMPILE_TEST
++ depends on OF
++
+ config PCIE_BCM6328
+ bool "BCM6328 PCIe controller"
+ depends on BMIPS_GENERIC || COMPILE_TEST
+--- a/drivers/pci/controller/Makefile
++++ b/drivers/pci/controller/Makefile
+@@ -1,4 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_PCIE_BCM6318) += pcie-bcm6318.o
+ obj-$(CONFIG_PCIE_BCM6328) += pcie-bcm6328.o
+ obj-$(CONFIG_PCIE_CADENCE) += cadence/
+ obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o
--- /dev/null
+--- a/drivers/pci/controller/Kconfig
++++ b/drivers/pci/controller/Kconfig
+@@ -3,6 +3,11 @@
+ menu "PCI controller drivers"
+ depends on PCI
+
++config PCI_BCM6348
++ bool "BCM6348 PCI controller"
++ depends on BMIPS_GENERIC || COMPILE_TEST
++ depends on OF
++
+ config PCIE_BCM6318
+ bool "BCM6318 PCIe controller"
+ depends on BMIPS_GENERIC || COMPILE_TEST
+--- a/drivers/pci/controller/Makefile
++++ b/drivers/pci/controller/Makefile
+@@ -1,4 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_PCI_BCM6348) += pci-bcm6348.o
+ obj-$(CONFIG_PCIE_BCM6318) += pcie-bcm6318.o
+ obj-$(CONFIG_PCIE_BCM6328) += pcie-bcm6328.o
+ obj-$(CONFIG_PCIE_CADENCE) += cadence/
projects / openwrt / staging / zorun.git / commitdiff