drm/amdgpu/UVD: set no_user_fence flag to true
authorLeo Liu <leo.liu@amd.com>
Wed, 8 May 2019 15:07:26 +0000 (11:07 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 24 May 2019 17:20:51 +0000 (12:20 -0500)
There is no user fence support for UVD

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

index c4fb58667fd451c8157398022735a1c35a568a3d..bf3385280d3f6e429ac721909d429457f6ea5e52 100644 (file)
@@ -741,6 +741,7 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
        .type = AMDGPU_RING_TYPE_UVD,
        .align_mask = 0xf,
        .support_64bit_ptrs = false,
+       .no_user_fence = true,
        .get_rptr = uvd_v4_2_ring_get_rptr,
        .get_wptr = uvd_v4_2_ring_get_wptr,
        .set_wptr = uvd_v4_2_ring_set_wptr,
index 52bd8a6547347e287e18c916ae6e07517f2039a3..3210a7bd9a6d693183c0e0334d9120346805bd00 100644 (file)
@@ -849,6 +849,7 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
        .type = AMDGPU_RING_TYPE_UVD,
        .align_mask = 0xf,
        .support_64bit_ptrs = false,
+       .no_user_fence = true,
        .get_rptr = uvd_v5_0_ring_get_rptr,
        .get_wptr = uvd_v5_0_ring_get_wptr,
        .set_wptr = uvd_v5_0_ring_set_wptr,
index c9edddf9f88a8c67ce9742632120287504838b68..c61a314c56cc3aaaf403111802c5d38385f67aaa 100644 (file)
@@ -1502,6 +1502,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
        .type = AMDGPU_RING_TYPE_UVD,
        .align_mask = 0xf,
        .support_64bit_ptrs = false,
+       .no_user_fence = true,
        .get_rptr = uvd_v6_0_ring_get_rptr,
        .get_wptr = uvd_v6_0_ring_get_wptr,
        .set_wptr = uvd_v6_0_ring_set_wptr,
@@ -1527,6 +1528,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
        .type = AMDGPU_RING_TYPE_UVD,
        .align_mask = 0xf,
        .support_64bit_ptrs = false,
+       .no_user_fence = true,
        .get_rptr = uvd_v6_0_ring_get_rptr,
        .get_wptr = uvd_v6_0_ring_get_wptr,
        .set_wptr = uvd_v6_0_ring_set_wptr,
@@ -1555,6 +1557,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
        .align_mask = 0x3f,
        .nop = HEVC_ENC_CMD_NO_OP,
        .support_64bit_ptrs = false,
+       .no_user_fence = true,
        .get_rptr = uvd_v6_0_enc_ring_get_rptr,
        .get_wptr = uvd_v6_0_enc_ring_get_wptr,
        .set_wptr = uvd_v6_0_enc_ring_set_wptr,
index 2191d3d0a2190a4cbe5ac93835b2ab753f393c61..cdb96d4cb424591c57fa10288494010c8c1abfb3 100644 (file)
@@ -1759,6 +1759,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
        .type = AMDGPU_RING_TYPE_UVD,
        .align_mask = 0xf,
        .support_64bit_ptrs = false,
+       .no_user_fence = true,
        .vmhub = AMDGPU_MMHUB,
        .get_rptr = uvd_v7_0_ring_get_rptr,
        .get_wptr = uvd_v7_0_ring_get_wptr,
@@ -1791,6 +1792,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
        .align_mask = 0x3f,
        .nop = HEVC_ENC_CMD_NO_OP,
        .support_64bit_ptrs = false,
+       .no_user_fence = true,
        .vmhub = AMDGPU_MMHUB,
        .get_rptr = uvd_v7_0_enc_ring_get_rptr,
        .get_wptr = uvd_v7_0_enc_ring_get_wptr,