MIPS: remove CONFIG_DMA_COHERENT

We can just check for !CONFIG_DMA_NONCOHERENT instead and simplify things
a lot.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/19530/
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: David Daney <david.daney@cavium.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tom Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: iommu@lists.linux-foundation.org
Cc: linux-mips@linux-mips.org

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 08c10c518f8323fea7838d92fe03b748cbb2966e..a7ecd785f8b9cdc13c65a873748ded30057e7b85 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -666,7 +666,6 @@ config SGI_IP27
        select FW_ARC64
        select BOOT_ELF64
        select DEFAULT_SGI_PARTITION
-       select DMA_COHERENT
        select SYS_HAS_EARLY_PRINTK
        select HW_HAS_PCI
        select NR_CPUS_DEFAULT_64
@@ -743,7 +742,6 @@ config SGI_IP32
 config SIBYTE_CRHINE
        bool "Sibyte BCM91120C-CRhine"
        select BOOT_ELF32
-       select DMA_COHERENT
        select SIBYTE_BCM1120
        select SWAP_IO_SPACE
        select SYS_HAS_CPU_SB1
@@ -753,7 +751,6 @@ config SIBYTE_CRHINE
 config SIBYTE_CARMEL
        bool "Sibyte BCM91120x-Carmel"
        select BOOT_ELF32
-       select DMA_COHERENT
        select SIBYTE_BCM1120
        select SWAP_IO_SPACE
        select SYS_HAS_CPU_SB1
@@ -763,7 +760,6 @@ config SIBYTE_CARMEL
 config SIBYTE_CRHONE
        bool "Sibyte BCM91125C-CRhone"
        select BOOT_ELF32
-       select DMA_COHERENT
        select SIBYTE_BCM1125
        select SWAP_IO_SPACE
        select SYS_HAS_CPU_SB1
@@ -774,7 +770,6 @@ config SIBYTE_CRHONE
 config SIBYTE_RHONE
        bool "Sibyte BCM91125E-Rhone"
        select BOOT_ELF32
-       select DMA_COHERENT
        select SIBYTE_BCM1125H
        select SWAP_IO_SPACE
        select SYS_HAS_CPU_SB1
@@ -784,7 +779,6 @@ config SIBYTE_RHONE
 config SIBYTE_SWARM
        bool "Sibyte BCM91250A-SWARM"
        select BOOT_ELF32
-       select DMA_COHERENT
        select HAVE_PATA_PLATFORM
        select SIBYTE_SB1250
        select SWAP_IO_SPACE
@@ -797,7 +791,6 @@ config SIBYTE_SWARM
 config SIBYTE_LITTLESUR
        bool "Sibyte BCM91250C2-LittleSur"
        select BOOT_ELF32
-       select DMA_COHERENT
        select HAVE_PATA_PLATFORM
        select SIBYTE_SB1250
        select SWAP_IO_SPACE
@@ -809,7 +802,6 @@ config SIBYTE_LITTLESUR
 config SIBYTE_SENTOSA
        bool "Sibyte BCM91250E-Sentosa"
        select BOOT_ELF32
-       select DMA_COHERENT
        select SIBYTE_SB1250
        select SWAP_IO_SPACE
        select SYS_HAS_CPU_SB1
@@ -819,7 +811,6 @@ config SIBYTE_SENTOSA
 config SIBYTE_BIGSUR
        bool "Sibyte BCM91480B-BigSur"
        select BOOT_ELF32
-       select DMA_COHERENT
        select NR_CPUS_DEFAULT_4
        select SIBYTE_BCM1x80
        select SWAP_IO_SPACE
@@ -896,7 +887,6 @@ config CAVIUM_OCTEON_SOC
        select CEVT_R4K
        select ARCH_HAS_PHYS_TO_DMA
        select PHYS_ADDR_T_64BIT
-       select DMA_COHERENT
        select SYS_SUPPORTS_64BIT_KERNEL
        select SYS_SUPPORTS_BIG_ENDIAN
        select EDAC_SUPPORT
@@ -945,7 +935,6 @@ config NLM_XLR_BOARD
        select PHYS_ADDR_T_64BIT
        select SYS_SUPPORTS_BIG_ENDIAN
        select SYS_SUPPORTS_HIGHMEM
-       select DMA_COHERENT
        select NR_CPUS_DEFAULT_32
        select CEVT_R4K
        select CSRC_R4K
@@ -973,7 +962,6 @@ config NLM_XLP_BOARD
        select SYS_SUPPORTS_BIG_ENDIAN
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_SUPPORTS_HIGHMEM
-       select DMA_COHERENT
        select NR_CPUS_DEFAULT_32
        select CEVT_R4K
        select CSRC_R4K
@@ -992,7 +980,6 @@ config MIPS_PARAVIRT
        bool "Para-Virtualized guest system"
        select CEVT_R4K
        select CSRC_R4K
-       select DMA_COHERENT
        select SYS_SUPPORTS_64BIT_KERNEL
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_BIG_ENDIAN
@@ -1118,9 +1105,6 @@ config DMA_PERDEV_COHERENT
        bool
        select DMA_MAYBE_COHERENT
 
-config DMA_COHERENT
-       bool
-
 config DMA_NONCOHERENT
        bool
        select NEED_DMA_MAP_STATE

diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h
index 72d0eab02afcbbfc33bd6ee653389a30887c1f3a..8eda48748ed59cc9d2e57bc19acb41ebacb853ae 100644 (file)
--- a/arch/mips/include/asm/dma-coherence.h
+++ b/arch/mips/include/asm/dma-coherence.h
@@ -21,10 +21,10 @@ enum coherent_io_user_state {
 extern enum coherent_io_user_state coherentio;
 extern int hw_coherentio;
 #else
-#ifdef CONFIG_DMA_COHERENT
-#define coherentio     IO_COHERENCE_ENABLED
-#else
+#ifdef CONFIG_DMA_NONCOHERENT
 #define coherentio     IO_COHERENCE_DISABLED
+#else
+#define coherentio     IO_COHERENCE_ENABLED
 #endif
 #define hw_coherentio  0
 #endif /* CONFIG_DMA_MAYBE_COHERENT */

diff --git a/arch/mips/include/asm/mach-generic/kmalloc.h b/arch/mips/include/asm/mach-generic/kmalloc.h
index 74207c7bd00d9b51c98991e83d3d865cc51767bc..649a98338886cd9f27cc4091df8e4ecc52b6a62c 100644 (file)
--- a/arch/mips/include/asm/mach-generic/kmalloc.h
+++ b/arch/mips/include/asm/mach-generic/kmalloc.h
@@ -2,8 +2,7 @@
 #ifndef __ASM_MACH_GENERIC_KMALLOC_H
 #define __ASM_MACH_GENERIC_KMALLOC_H
 
-
-#ifndef CONFIG_DMA_COHERENT
+#ifdef CONFIG_DMA_NONCOHERENT
 /*
  * Total overkill for most systems but need as a safe default.
  * Set this one if any device in the system might do non-coherent DMA.

diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index 7b63914d2e58e0efb17abf011b37c800428e8914..4d5cdfeee3db8b0534635ab40c1b6ce8b38f65b2 100644 (file)
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -227,7 +227,7 @@ static void __init bonito_quirks_setup(void)
        } else
                BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
 
-#ifdef CONFIG_DMA_COHERENT
+#ifndef CONFIG_DMA_NONCOHERENT
        if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
                BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
                pr_info("Enabled Bonito CPU coherency\n");
@@ -279,7 +279,7 @@ void __init plat_mem_setup(void)
         */
        enable_dma(4);
 
-#ifdef CONFIG_DMA_COHERENT
+#ifndef CONFIG_DMA_NONCOHERENT
        if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
                panic("Hardware DMA cache coherency not supported");
 #endif

diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index f4dbce25bc6a5791da300045ca97038443dc49da..7ec278d720966c533a31e9945313c6d07853720d 100644 (file)
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -70,7 +70,6 @@ config SIBYTE_BCM1x55
 
 config SIBYTE_SB1xxx_SOC
        bool
-       select DMA_COHERENT
        select IRQ_MIPS_CPU
        select SWAP_IO_SPACE
        select SYS_SUPPORTS_32BIT_KERNEL