drm/amd/pp: Switch the tolerable latency for display

Select the lowest MCLK frequency that is within
the tolerable latency defined in DISPALY

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 7fdd9ede96c79b40123b2bba019f2fa223cfa451..e5b3abffefb6396ee814cd403205bb4ba3809d1e 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3217,7 +3217,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
                /* Find the lowest MCLK frequency that is within
                 * the tolerable latency defined in DAL
                 */
-               latency = 0;
+               latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
                for (i = 0; i < data->mclk_latency_table.count; i++) {
                        if ((data->mclk_latency_table.entries[i].latency <= latency) &&
                                (data->mclk_latency_table.entries[i].frequency >=