full_pipe_count = core_dc->res_pool->pipe_count;
if (core_dc->res_pool->underlay_pipe_index >= 0)
full_pipe_count--;
- core_dc->public.caps.max_targets = dm_min(
+ core_dc->public.caps.max_targets = min(
full_pipe_count,
core_dc->res_pool->stream_enc_count);
/* Make sure requested clock isn't lower than minimum threshold*/
if (requested_clk_khz > 0)
- requested_clk_khz = dm_max(requested_clk_khz,
+ requested_clk_khz = max(requested_clk_khz,
clk_dce->dentist_vco_freq_khz / 64);
/* Prepare to program display clock*/
/* Make sure requested clock isn't lower than minimum threshold*/
if (requested_clk_khz > 0)
- requested_clk_khz = dm_max(requested_clk_khz,
+ requested_clk_khz = max(requested_clk_khz,
clk_dce->dentist_vco_freq_khz / 62);
dce_clk_params.target_clock_frequency = requested_clk_khz;
#define dm_vlog(fmt, args) vprintk(fmt, args)
-#define dm_min(x, y) min(x, y)
-#define dm_max(x, y) max(x, y)
#endif