x86: BayTrail: southcluster.asl: Change PCI 64 bit address range / region

To allow bigger 64 bit prefetchable PCI regions in Linux, this patch
changes the base address and range of the ACPI area passed to Linux.
BayTrail can only physically access 36 bit of PCI address space. So
just chaning the range without changing the base address won't work
here, as 0xf.ffff.ffff is already the maximum address.

With this patch, a maximum of 16 GiB of local DDR is supported. This
should be enough for all BayTrail boards though.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
index dfc768cf7f8df12ce1cbf9f6043e5a260811c545..2a1c31cdc4a2e178d7b4a5cdbc7f22939a3714a7 100644 (file)
--- a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
@@ -150,9 +150,9 @@ Device (PCI0)
                CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
                CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
 
-               /* Set base address to 48GB and allocate 16GB for PCI space */
-               Store(0xc00000000, UMIN)
-               Store(0x400000000, ULEN)
+               /* Set base address to 16GB and allocate 48GB for PCI space */
+               Store(0x400000000, UMIN)
+               Store(0xc00000000, ULEN)
                Add(UMIN, Subtract(ULEN, 1), UMAX)
 
                Return (MCRS)