Replace downstream bmips RAC fixes with upstream patches.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
[backport upstream patches]
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ mips-cbr-reg = <0xff400000>;
mips-hpt-frequency = <150000000>;
cpu@0 {
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ mips-cbr-reg = <0xff400000>;
mips-hpt-frequency = <200000000>;
cpu@0 {
--- /dev/null
+From ce5cdd3b05216b704a704f466fb4c2dff3778caf Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 11 Jun 2024 13:35:33 +0200
+Subject: [PATCH] mips: bmips: BCM6358: make sure CBR is correctly set
+
+It was discovered that some device have CBR address set to 0 causing
+kernel panic when arch_sync_dma_for_cpu_all is called.
+
+This was notice in situation where the system is booted from TP1 and
+BMIPS_GET_CBR() returns 0 instead of a valid address and
+!!(read_c0_brcm_cmt_local() & (1 << 31)); not failing.
+
+The current check whether RAC flush should be disabled or not are not
+enough hence lets check if CBR is a valid address or not.
+
+Fixes: ab327f8acdf8 ("mips: bmips: BCM6358: disable RAC flush for TP1")
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/bmips/setup.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bmips/setup.c
++++ b/arch/mips/bmips/setup.c
+@@ -110,7 +110,8 @@ static void bcm6358_quirks(void)
+ * RAC flush causes kernel panics on BCM6358 when booting from TP1
+ * because the bootloader is not initializing it properly.
+ */
+- bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31));
++ bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) ||
++ !!BMIPS_GET_CBR();
+ }
+
+ static void bcm6368_quirks(void)
--- /dev/null
+From a5c05453a13ab324ad8719e8a23dfb6af01f3652 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 20 Jun 2024 17:26:42 +0200
+Subject: [PATCH 1/4] mips: bmips: rework and cache CBR addr handling
+
+Rework the handling of the CBR address and cache it. This address
+doesn't change and can be cached instead of reading the register every
+time.
+
+This is in preparation of permitting to tweak the CBR address in DT with
+broken SoC or bootloader.
+
+bmips_cbr_addr is defined in setup.c for each arch to keep compatibility
+with legacy brcm47xx/brcm63xx and generic BMIPS target.
+
+Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/bcm47xx/prom.c | 3 +++
+ arch/mips/bcm47xx/setup.c | 4 ++++
+ arch/mips/bcm63xx/prom.c | 3 +++
+ arch/mips/bcm63xx/setup.c | 4 ++++
+ arch/mips/bmips/dma.c | 2 +-
+ arch/mips/bmips/setup.c | 7 ++++++-
+ arch/mips/include/asm/bmips.h | 1 +
+ arch/mips/kernel/smp-bmips.c | 4 ++--
+ 8 files changed, 24 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/bcm47xx/prom.c
++++ b/arch/mips/bcm47xx/prom.c
+@@ -32,6 +32,7 @@
+ #include <linux/ssb/ssb_driver_chipcommon.h>
+ #include <linux/ssb/ssb_regs.h>
+ #include <linux/smp.h>
++#include <asm/bmips.h>
+ #include <asm/bootinfo.h>
+ #include <bcm47xx.h>
+ #include <bcm47xx_board.h>
+@@ -109,6 +110,8 @@ static __init void prom_init_mem(void)
+
+ void __init prom_init(void)
+ {
++ /* Cache CBR addr before CPU/DMA setup */
++ bmips_cbr_addr = BMIPS_GET_CBR();
+ prom_init_mem();
+ setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0);
+ }
+--- a/arch/mips/bcm47xx/setup.c
++++ b/arch/mips/bcm47xx/setup.c
+@@ -37,6 +37,7 @@
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_embedded.h>
+ #include <linux/bcma/bcma_soc.h>
++#include <asm/bmips.h>
+ #include <asm/bootinfo.h>
+ #include <asm/idle.h>
+ #include <asm/prom.h>
+@@ -45,6 +46,9 @@
+ #include <bcm47xx.h>
+ #include <bcm47xx_board.h>
+
++/* CBR addr doesn't change and we can cache it */
++void __iomem *bmips_cbr_addr __read_mostly;
++
+ union bcm47xx_bus bcm47xx_bus;
+ EXPORT_SYMBOL(bcm47xx_bus);
+
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -22,6 +22,9 @@ void __init prom_init(void)
+ {
+ u32 reg, mask;
+
++ /* Cache CBR addr before CPU/DMA setup */
++ bmips_cbr_addr = BMIPS_GET_CBR();
++
+ bcm63xx_cpu_init();
+
+ /* stop any running watchdog */
+--- a/arch/mips/bcm63xx/setup.c
++++ b/arch/mips/bcm63xx/setup.c
+@@ -12,6 +12,7 @@
+ #include <linux/memblock.h>
+ #include <linux/ioport.h>
+ #include <linux/pm.h>
++#include <asm/bmips.h>
+ #include <asm/bootinfo.h>
+ #include <asm/time.h>
+ #include <asm/reboot.h>
+@@ -22,6 +23,9 @@
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_gpio.h>
+
++/* CBR addr doesn't change and we can cache it */
++void __iomem *bmips_cbr_addr __read_mostly;
++
+ void bcm63xx_machine_halt(void)
+ {
+ pr_info("System halted\n");
+--- a/arch/mips/bmips/dma.c
++++ b/arch/mips/bmips/dma.c
+@@ -9,7 +9,7 @@ bool bmips_rac_flush_disable;
+
+ void arch_sync_dma_for_cpu_all(void)
+ {
+- void __iomem *cbr = BMIPS_GET_CBR();
++ void __iomem *cbr = bmips_cbr_addr;
+ u32 cfg;
+
+ if (boot_cpu_type() != CPU_BMIPS3300 &&
+--- a/arch/mips/bmips/setup.c
++++ b/arch/mips/bmips/setup.c
+@@ -34,6 +34,9 @@
+ #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
+ #define BCM6328_TP1_DISABLED BIT(9)
+
++/* CBR addr doesn't change and we can cache it */
++void __iomem *bmips_cbr_addr __read_mostly;
++
+ extern bool bmips_rac_flush_disable;
+
+ static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
+@@ -111,7 +114,7 @@ static void bcm6358_quirks(void)
+ * because the bootloader is not initializing it properly.
+ */
+ bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) ||
+- !!BMIPS_GET_CBR();
++ !!bmips_cbr_addr;
+ }
+
+ static void bcm6368_quirks(void)
+@@ -144,6 +147,8 @@ static void __init bmips_init_cfe(void)
+
+ void __init prom_init(void)
+ {
++ /* Cache CBR addr before CPU/DMA setup */
++ bmips_cbr_addr = BMIPS_GET_CBR();
+ bmips_init_cfe();
+ bmips_cpu_setup();
+ register_bmips_smp_ops();
+--- a/arch/mips/include/asm/bmips.h
++++ b/arch/mips/include/asm/bmips.h
+@@ -81,6 +81,7 @@ extern char bmips_smp_movevec[];
+ extern char bmips_smp_int_vec[];
+ extern char bmips_smp_int_vec_end[];
+
++extern void __iomem *bmips_cbr_addr;
+ extern int bmips_smp_enabled;
+ extern int bmips_cpu_offset;
+ extern cpumask_t bmips_booted_mask;
+--- a/arch/mips/kernel/smp-bmips.c
++++ b/arch/mips/kernel/smp-bmips.c
+@@ -518,7 +518,7 @@ static void bmips_set_reset_vec(int cpu,
+ info.val = val;
+ bmips_set_reset_vec_remote(&info);
+ } else {
+- void __iomem *cbr = BMIPS_GET_CBR();
++ void __iomem *cbr = bmips_cbr_addr;
+
+ if (cpu == 0)
+ __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
+@@ -591,7 +591,7 @@ asmlinkage void __weak plat_wired_tlb_se
+
+ void bmips_cpu_setup(void)
+ {
+- void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
++ void __iomem __maybe_unused *cbr = bmips_cbr_addr;
+ u32 __maybe_unused cfg;
+
+ switch (current_cpu_type()) {
--- /dev/null
+From b95b30e50aed225d26e20737873ae2404941901c Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 20 Jun 2024 17:26:44 +0200
+Subject: [PATCH 3/4] mips: bmips: setup: make CBR address configurable
+
+Add support to provide CBR address from DT to handle broken
+SoC/Bootloader that doesn't correctly init it. This permits to use the
+RAC flush even in these condition.
+
+To provide a CBR address from DT, the property "brcm,bmips-cbr-reg"
+needs to be set in the "cpus" node. On DT init, this property presence
+will be checked and will set the bmips_cbr_addr value accordingly. Also
+bmips_rac_flush_disable will be set to false as RAC flush can be
+correctly supported.
+
+The CBR address from DT will overwrite the cached one and the
+one set in the CBR register will be ignored.
+
+Also the DT CBR address is validated on being outside DRAM window.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/bcm47xx/setup.c | 6 +++++-
+ arch/mips/bcm63xx/setup.c | 6 +++++-
+ arch/mips/bmips/setup.c | 30 ++++++++++++++++++++++++++++--
+ 3 files changed, 38 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/bcm47xx/setup.c
++++ b/arch/mips/bcm47xx/setup.c
+@@ -46,7 +46,11 @@
+ #include <bcm47xx.h>
+ #include <bcm47xx_board.h>
+
+-/* CBR addr doesn't change and we can cache it */
++/*
++ * CBR addr doesn't change and we can cache it.
++ * For broken SoC/Bootloader CBR addr might also be provided via DT
++ * with "brcm,bmips-cbr-reg" in the "cpus" node.
++ */
+ void __iomem *bmips_cbr_addr __read_mostly;
+
+ union bcm47xx_bus bcm47xx_bus;
+--- a/arch/mips/bcm63xx/setup.c
++++ b/arch/mips/bcm63xx/setup.c
+@@ -23,7 +23,11 @@
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_gpio.h>
+
+-/* CBR addr doesn't change and we can cache it */
++/*
++ * CBR addr doesn't change and we can cache it.
++ * For broken SoC/Bootloader CBR addr might also be provided via DT
++ * with "brcm,bmips-cbr-reg" in the "cpus" node.
++ */
+ void __iomem *bmips_cbr_addr __read_mostly;
+
+ void bcm63xx_machine_halt(void)
+--- a/arch/mips/bmips/setup.c
++++ b/arch/mips/bmips/setup.c
+@@ -34,7 +34,11 @@
+ #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
+ #define BCM6328_TP1_DISABLED BIT(9)
+
+-/* CBR addr doesn't change and we can cache it */
++/*
++ * CBR addr doesn't change and we can cache it.
++ * For broken SoC/Bootloader CBR addr might also be provided via DT
++ * with "brcm,bmips-cbr-reg" in the "cpus" node.
++ */
+ void __iomem *bmips_cbr_addr __read_mostly;
+
+ extern bool bmips_rac_flush_disable;
+@@ -208,13 +212,35 @@ void __init plat_mem_setup(void)
+ void __init device_tree_init(void)
+ {
+ struct device_node *np;
++ u32 addr;
+
+ unflatten_and_copy_device_tree();
+
+ /* Disable SMP boot unless both CPUs are listed in DT and !disabled */
+ np = of_find_node_by_name(NULL, "cpus");
+- if (np && of_get_available_child_count(np) <= 1)
++ if (!np)
++ return;
++
++ if (of_get_available_child_count(np) <= 1)
+ bmips_smp_enabled = 0;
++
++ /* Check if DT provide a CBR address */
++ if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr))
++ goto exit;
++
++ /* Make sure CBR address is outside DRAM window */
++ if (addr >= (u32)memblock_start_of_DRAM() &&
++ addr < (u32)memblock_end_of_DRAM()) {
++ WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n",
++ addr);
++ goto exit;
++ }
++
++ bmips_cbr_addr = (void __iomem *)addr;
++ /* Since CBR is provided by DT, enable RAC flush */
++ bmips_rac_flush_disable = false;
++
++exit:
+ of_node_put(np);
+ }
+
--- /dev/null
+From 04f38d1a4db017f17e82442727b91ce03dd72759 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Daniel=20Gonz=C3=A1lez=20Cabanelas?= <dgcbueu@gmail.com>
+Date: Thu, 20 Jun 2024 17:26:45 +0200
+Subject: [PATCH 4/4] mips: bmips: enable RAC on BMIPS4350
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The data RAC is left disabled by the bootloader in some SoCs, at least in
+the core it boots from.
+Enabling this feature increases the performance up to +30% depending on the
+task.
+
+Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
+Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
+[ rework code and reduce code duplication ]
+Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/kernel/smp-bmips.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+--- a/arch/mips/kernel/smp-bmips.c
++++ b/arch/mips/kernel/smp-bmips.c
+@@ -592,6 +592,7 @@ asmlinkage void __weak plat_wired_tlb_se
+ void bmips_cpu_setup(void)
+ {
+ void __iomem __maybe_unused *cbr = bmips_cbr_addr;
++ u32 __maybe_unused rac_addr;
+ u32 __maybe_unused cfg;
+
+ switch (current_cpu_type()) {
+@@ -620,6 +621,23 @@ void bmips_cpu_setup(void)
+ __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
+ break;
+
++ case CPU_BMIPS4350:
++ rac_addr = BMIPS_RAC_CONFIG_1;
++
++ if (!(read_c0_brcm_cmt_local() & (1 << 31)))
++ rac_addr = BMIPS_RAC_CONFIG;
++
++ /* Enable data RAC */
++ cfg = __raw_readl(cbr + rac_addr);
++ __raw_writel(cfg | 0xf, cbr + rac_addr);
++ __raw_readl(cbr + rac_addr);
++
++ /* Flush stale data out of the readahead cache */
++ cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
++ __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
++ __raw_readl(cbr + BMIPS_RAC_CONFIG);
++ break;
++
+ case CPU_BMIPS4380:
+ /* CBG workaround for early BMIPS4380 CPUs */
+ switch (read_c0_prid()) {
--- a/arch/mips/bmips/setup.c
+++ b/arch/mips/bmips/setup.c
-@@ -31,13 +31,52 @@
+@@ -31,8 +31,42 @@
#define RELO_NORMAL_VEC BIT(18)
+#define BCM63268_FCVO_SHIFT 21
+#define BCM63268_FCVO_MASK (0xf << BCM63268_FCVO_SHIFT)
- extern bool bmips_rac_flush_disable;
+ /*
+ * CBR addr doesn't change and we can cache it.
+@@ -45,6 +79,11 @@ extern bool bmips_rac_flush_disable;
static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
struct bmips_quirk {
const char *compatible;
void (*quirk_fn)(void);
-@@ -153,17 +192,161 @@ const char *get_system_type(void)
+@@ -163,17 +202,161 @@ const char *get_system_type(void)
return "Generic BMIPS kernel";
}
+
+#define DDR_CSEND_REG 0x8
- extern bool bmips_rac_flush_disable;
-
-@@ -77,6 +98,11 @@ struct bmips_cpufreq {
+ /*
+ * CBR addr doesn't change and we can cache it.
+@@ -84,6 +105,11 @@ struct bmips_cpufreq {
u32 (*cpu_freq)(void);
};
struct bmips_quirk {
const char *compatible;
void (*quirk_fn)(void);
-@@ -351,9 +377,90 @@ void __init plat_time_init(void)
+@@ -361,9 +387,90 @@ void __init plat_time_init(void)
mips_hpt_frequency = freq;
}
const struct bmips_quirk *q;
set_io_port_base(0);
-@@ -374,6 +481,18 @@ void __init plat_mem_setup(void)
+@@ -384,6 +491,18 @@ void __init plat_mem_setup(void)
__dt_setup_arch(dtb);
+++ /dev/null
-From 3e4c3863e0cfb8c2abdff6bb494ca69d3d2aed9c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
-Date: Sat, 10 Jun 2023 17:01:40 +0200
-Subject: [PATCH] mips: bmips: dma: fix CBR address
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Some BCM63xx SoCs may return CBR address as 0.
-
-Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
----
- arch/mips/bmips/dma.c | 12 ++++--------
- arch/mips/bmips/setup.c | 11 ++++-------
- 2 files changed, 8 insertions(+), 15 deletions(-)
-
---- a/arch/mips/bmips/dma.c
-+++ b/arch/mips/bmips/dma.c
-@@ -5,11 +5,10 @@
- #include <asm/bmips.h>
- #include <asm/io.h>
-
--bool bmips_rac_flush_disable;
-+void __iomem *bmips_cbr_addr;
-
- void arch_sync_dma_for_cpu_all(void)
- {
-- void __iomem *cbr = BMIPS_GET_CBR();
- u32 cfg;
-
- if (boot_cpu_type() != CPU_BMIPS3300 &&
-@@ -17,11 +16,8 @@ void arch_sync_dma_for_cpu_all(void)
- boot_cpu_type() != CPU_BMIPS4380)
- return;
-
-- if (unlikely(bmips_rac_flush_disable))
-- return;
--
- /* Flush stale data out of the readahead cache */
-- cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
-- __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
-- __raw_readl(cbr + BMIPS_RAC_CONFIG);
-+ cfg = __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG);
-+ __raw_writel(cfg | 0x100, bmips_cbr_addr + BMIPS_RAC_CONFIG);
-+ __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG);
- }
---- a/arch/mips/bmips/setup.c
-+++ b/arch/mips/bmips/setup.c
-@@ -89,7 +89,7 @@
-
- #define DDR_CSEND_REG 0x8
-
--extern bool bmips_rac_flush_disable;
-+extern void __iomem *bmips_cbr_addr;
-
- static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
-
-@@ -170,12 +170,6 @@ static void bcm6358_quirks(void)
- * disable SMP for now
- */
- bmips_smp_enabled = 0;
--
-- /*
-- * RAC flush causes kernel panics on BCM6358 when booting from TP1
-- * because the bootloader is not initializing it properly.
-- */
-- bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31));
- }
-
- static void bcm6368_quirks(void)
-@@ -208,6 +202,11 @@ static void __init bmips_init_cfe(void)
-
- void __init prom_init(void)
- {
-+ if (!(read_c0_brcm_cbr() >> 18))
-+ bmips_cbr_addr = (void __iomem *) 0xff400000;
-+ else
-+ bmips_cbr_addr = BMIPS_GET_CBR();
-+
- bmips_init_cfe();
- bmips_cpu_setup();
- register_bmips_smp_ops();
+++ /dev/null
-From 7f862eaedac56b67972393f0a9affcd2fe53479b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Daniel=20Gonz=C3=A1lez=20Cabanelas?= <dgcbueu@gmail.com>
-Date: Sun, 18 Jun 2023 19:59:25 +0200
-Subject: [PATCH] mips: bmips: enable RAC on BMIPS4350
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The data RAC is left disabled by the bootloader in some SoCs, at least in
-the core it boots from.
-Enabling this feature increases the performance up to +30% depending on the
-task.
-
-Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
-Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
----
- arch/mips/kernel/smp-bmips.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/mips/kernel/smp-bmips.c
-+++ b/arch/mips/kernel/smp-bmips.c
-@@ -620,6 +620,20 @@ void bmips_cpu_setup(void)
- __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
- break;
-
-+ case CPU_BMIPS4350:
-+ /* Enable data RAC */
-+ if (!(read_c0_brcm_cmt_local() & (1 << 31))) {
-+ cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
-+ __raw_writel(cfg | 0xa, cbr + BMIPS_RAC_CONFIG);
-+ __raw_readl(cbr + BMIPS_RAC_CONFIG);
-+ } else {
-+ cbr = (void __iomem *)0xff400000;
-+ cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG_1);
-+ __raw_writel(cfg | 0xa, cbr + BMIPS_RAC_CONFIG_1);
-+ __raw_readl(cbr + BMIPS_RAC_CONFIG_1);
-+ }
-+ break;
-+
- case CPU_BMIPS4380:
- /* CBG workaround for early BMIPS4380 CPUs */
- switch (read_c0_prid()) {
projects / openwrt / staging / stintel.git / commitdiff