This patch adds syscon property for specifying soc-glue core.
Currently, soc-glue core is used for changing the state of S/PDIF
signal output pin to signal output state or Hi-Z state. After
resetting of SoC Hi-Z state is selected. This driver set to signal
output state when syscon property is available.
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
return rb_space_to_end(sub->wr_offs, sub->rd_offs, sub->compr_bytes);
}
+/**
+ * aio_iecout_set_enable - setup IEC output via SoC glue
+ * @chip: the AIO chip pointer
+ * @enable: false to stop the output, true to start
+ *
+ * Set enabled or disabled S/PDIF signal output to out of SoC via AOnIEC pins.
+ * This function need to call at driver startup.
+ *
+ * The regmap of SoC glue is specified by 'socionext,syscon' optional property
+ * of DT. This function has no effect if no property.
+ */
+void aio_iecout_set_enable(struct uniphier_aio_chip *chip, bool enable)
+{
+ struct regmap *r = chip->regmap_sg;
+
+ if (!r)
+ return;
+
+ regmap_write(r, SG_AOUTEN, (enable) ? ~0 : 0);
+}
+
/**
* aio_chip_set_pll - set frequency to audio PLL
* @chip : the AIO chip pointer
#include <linux/clk.h>
#include <linux/errno.h>
#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
sub->spec = spec;
}
+ aio_iecout_set_enable(aio->chip, true);
aio_chip_init(aio->chip);
aio->chip->active = 1;
if (ret)
goto err_out_clock;
+ aio_iecout_set_enable(aio->chip, true);
aio_chip_init(aio->chip);
for (i = 0; i < ARRAY_SIZE(aio->sub); i++) {
if (!chip->chip_spec)
return -EINVAL;
+ chip->regmap_sg = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "socionext,syscon");
+ if (IS_ERR(chip->regmap_sg)) {
+ if (PTR_ERR(chip->regmap_sg) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+ chip->regmap_sg = NULL;
+ }
+
chip->clk = devm_clk_get(dev, "aio");
if (IS_ERR(chip->clk))
return PTR_ERR(chip->clk);
#include <linux/bitops.h>
+/* soc-glue */
+#define SG_AOUTEN 0x1c04
+
/* SW view */
#define A2CHNMAPCTR0(n) (0x00000 + 0x40 * (n))
#define A2RBNMAPCTR0(n) (0x01000 + 0x40 * (n))
struct clk *clk;
struct reset_control *rst;
struct regmap *regmap;
+ struct regmap *regmap_sg;
int active;
};
u64 aio_rb_space(struct uniphier_aio_sub *sub);
u64 aio_rb_space_to_end(struct uniphier_aio_sub *sub);
+void aio_iecout_set_enable(struct uniphier_aio_chip *chip, bool enable);
int aio_chip_set_pll(struct uniphier_aio_chip *chip, int pll_id,
unsigned int freq);
void aio_chip_init(struct uniphier_aio_chip *chip);