drm/radeon/kms: rework pll algo selection

Rework the pll algo selection so that the pll algo
in use can be selected more easily.  This allows
us to select different pll divider selection algos
for specific monitors that work better with one algo
or the other.  This is needed for the next patch which
adds an LVDS pll quirk for a specific notebook.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index af464e351fbd95da253435c00b9b3a43c877553c..4bae5511ea605b5e3b3f895771d43caaf39dcb4a 100644 (file)
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -424,6 +424,15 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
        /* reset the pll flags */
        pll->flags = 0;
 
+       /* select the PLL algo */
+       if (ASIC_IS_AVIVO(rdev)) {
+               if (radeon_new_pll)
+                       pll->algo = PLL_ALGO_AVIVO;
+               else
+                       pll->algo = PLL_ALGO_LEGACY;
+       } else
+               pll->algo = PLL_ALGO_LEGACY;
+
        if (ASIC_IS_AVIVO(rdev)) {
                if ((rdev->family == CHIP_RS600) ||
                    (rdev->family == CHIP_RS690) ||
@@ -452,6 +461,11 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                                /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
                                if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
                                        adjusted_clock = mode->clock * 2;
+                               /* LVDS PLL quirks */
+                               if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
+                                       struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
+                                       pll->algo = dig->pll_algo;
+                               }
                        } else {
                                if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
                                        pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
@@ -550,18 +564,8 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
        /* adjust pixel clock as needed */
        adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
 
-       if (ASIC_IS_AVIVO(rdev)) {
-               if (radeon_new_pll)
-                       radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock,
-                                                &fb_div, &frac_fb_div,
-                                                &ref_div, &post_div);
-               else
-                       radeon_compute_pll(pll, adjusted_clock, &pll_clock,
-                                          &fb_div, &frac_fb_div,
-                                          &ref_div, &post_div);
-       } else
-               radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
-                                  &ref_div, &post_div);
+       radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
+                          &ref_div, &post_div);
 
        index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,

diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index fa82ca74324e45be7fece1a947ea1ead50a5a77d..667f099e84af93ffd9662d5b972b17f91e678a4e 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1143,6 +1143,14 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
 
                lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
 
+               if (ASIC_IS_AVIVO(rdev)) {
+                       if (radeon_new_pll)
+                               lvds->pll_algo = PLL_ALGO_AVIVO;
+                       else
+                               lvds->pll_algo = PLL_ALGO_LEGACY;
+               } else
+                       lvds->pll_algo = PLL_ALGO_LEGACY;
+
                encoder->native_mode = lvds->native_mode;
        }
        return lvds;

diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 79634da7c31136f5a6db484d5de8955f9471126e..62fe66c023418602ded3dd7b61ee44b9a778947a 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -405,13 +405,13 @@ static inline uint32_t radeon_div(uint64_t n, uint32_t d)
        return n;
 }
 
-void radeon_compute_pll(struct radeon_pll *pll,
-                       uint64_t freq,
-                       uint32_t *dot_clock_p,
-                       uint32_t *fb_div_p,
-                       uint32_t *frac_fb_div_p,
-                       uint32_t *ref_div_p,
-                       uint32_t *post_div_p)
+static void radeon_compute_pll_legacy(struct radeon_pll *pll,
+                                     uint64_t freq,
+                                     uint32_t *dot_clock_p,
+                                     uint32_t *fb_div_p,
+                                     uint32_t *frac_fb_div_p,
+                                     uint32_t *ref_div_p,
+                                     uint32_t *post_div_p)
 {
        uint32_t min_ref_div = pll->min_ref_div;
        uint32_t max_ref_div = pll->max_ref_div;
@@ -571,13 +571,13 @@ void radeon_compute_pll(struct radeon_pll *pll,
        *post_div_p = best_post_div;
 }
 
-void radeon_compute_pll_avivo(struct radeon_pll *pll,
-                             uint64_t freq,
-                             uint32_t *dot_clock_p,
-                             uint32_t *fb_div_p,
-                             uint32_t *frac_fb_div_p,
-                             uint32_t *ref_div_p,
-                             uint32_t *post_div_p)
+static void radeon_compute_pll_avivo(struct radeon_pll *pll,
+                                    uint64_t freq,
+                                    uint32_t *dot_clock_p,
+                                    uint32_t *fb_div_p,
+                                    uint32_t *frac_fb_div_p,
+                                    uint32_t *ref_div_p,
+                                    uint32_t *post_div_p)
 {
        fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq;
        fixed20_12 pll_out_max, pll_out_min;
@@ -662,6 +662,27 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
        DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
 }
 
+void radeon_compute_pll(struct radeon_pll *pll,
+                       uint64_t freq,
+                       uint32_t *dot_clock_p,
+                       uint32_t *fb_div_p,
+                       uint32_t *frac_fb_div_p,
+                       uint32_t *ref_div_p,
+                       uint32_t *post_div_p)
+{
+       switch (pll->algo) {
+       case PLL_ALGO_AVIVO:
+               radeon_compute_pll_avivo(pll, freq, dot_clock_p, fb_div_p,
+                                        frac_fb_div_p, ref_div_p, post_div_p);
+               break;
+       case PLL_ALGO_LEGACY:
+       default:
+               radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p,
+                                         frac_fb_div_p, ref_div_p, post_div_p);
+               break;
+       }
+}
+
 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
 {
        struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);

diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index d6d69bb2eceaa56903ef62eb5cc91b3bc151a36a..83d4dbd6d067fe0cb16bb495a60d29aadcc7f728 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -703,6 +703,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                pll = &rdev->clock.p1pll;
 
        pll->flags = RADEON_PLL_LEGACY;
+       pll->algo = PLL_ALGO_LEGACY;
 
        if (mode->clock > 200000) /* range limits??? */
                pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;

diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 71439ba2feeb4e5f8af82e2a86fb4c3648373e86..d1e859d1dbf9ad4db84cad7ce09b4151e1e3fb65 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -113,6 +113,7 @@ struct radeon_tmds_pll {
 
 #define RADEON_MAX_BIOS_CONNECTOR 16
 
+/* pll flags */
 #define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
 #define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
 #define RADEON_PLL_USE_REF_DIV          (1 << 2)
@@ -127,6 +128,12 @@ struct radeon_tmds_pll {
 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
 #define RADEON_PLL_USE_POST_DIV         (1 << 12)
 
+/* pll algo */
+enum radeon_pll_algo {
+       PLL_ALGO_LEGACY,
+       PLL_ALGO_AVIVO
+};
+
 struct radeon_pll {
        /* reference frequency */
        uint32_t reference_freq;
@@ -157,6 +164,8 @@ struct radeon_pll {
 
        /* pll id */
        uint32_t id;
+       /* pll algo */
+       enum radeon_pll_algo algo;
 };
 
 struct i2c_algo_radeon_data {
@@ -309,6 +318,7 @@ struct radeon_encoder_atom_dig {
        /* atom lvds */
        uint32_t lvds_misc;
        uint16_t panel_pwr_delay;
+       enum radeon_pll_algo pll_algo;
        struct radeon_atom_ss *ss;
        /* panel mode */
        struct drm_display_mode native_mode;
@@ -439,14 +449,6 @@ extern void radeon_compute_pll(struct radeon_pll *pll,
                               uint32_t *ref_div_p,
                               uint32_t *post_div_p);
 
-extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
-                                    uint64_t freq,
-                                    uint32_t *dot_clock_p,
-                                    uint32_t *fb_div_p,
-                                    uint32_t *frac_fb_div_p,
-                                    uint32_t *ref_div_p,
-                                    uint32_t *post_div_p);
-
 extern void radeon_setup_encoder_clones(struct drm_device *dev);
 
 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);