ipq806x: add qpic nand and bam dma node's in ipq4019 dts tree

This change adds QPIC BAM dma and NAND driver node's in IPQ4019
device tree, also enable this for AP-DK04.1 based boards.

Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>

diff --git a/target/linux/ipq806x/patches-4.9/863-dts-ipq4019-add-nand-and-qpic-bam-dma-node.patch b/target/linux/ipq806x/patches-4.9/863-dts-ipq4019-add-nand-and-qpic-bam-dma-node.patch
new file mode 100644 (file)
index 0000000..44e162b
--- /dev/null
+++ b/target/linux/ipq806x/patches-4.9/863-dts-ipq4019-add-nand-and-qpic-bam-dma-node.patch
@@ -0,0 +1,172 @@
+From 02bbf3c46e1e38e9ca699143566903683e3a015d Mon Sep 17 00:00:00 2001
+From: Ram Chandra Jangir <rjangir@codeaurora.org>
+Date: Thu, 20 Apr 2017 10:45:00 +0530
+Subject: [PATCH] dts: ipq4019: add nand and qpic bam dma node
+
+This change adds QPIC BAM dma and NAND driver node's in
+IPQ4019 device tree, also enable this for AP-DK04.1 based
+boards.
+
+Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 75 +++++++++++++++++++++++++++
+ arch/arm/boot/dts/qcom-ipq4019.dtsi           | 38 ++++++++++++++
+ 2 files changed, 113 insertions(+)
+
+diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
+index 09fb047..e94954e 100644
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
+@@ -101,6 +101,86 @@
+                                       bias-bus-hold;
+                               };
+                       };
++
++                      nand_pins: nand_pins {
++
++                               mux_1 {
++                                       pins = "gpio52", "gpio53", "gpio54",
++                                              "gpio55", "gpio56", "gpio61",
++                                              "gpio62", "gpio63", "gpio69";
++                                       function = "qpic_pad";
++                                       bias-disable;
++                               };
++
++                              mux_2 {
++                                      pins = "gpio67";
++                                      function = "qpic_pad0";
++                                      bias-disable;
++                              };
++
++                              mux_3 {
++                                      pins = "gpio64";
++                                      function = "qpic_pad1";
++                                      bias-disable;
++                              };
++
++                              mux_4 {
++                                      pins = "gpio65";
++                                      function = "qpic_pad2";
++                                      bias-disable;
++                              };
++
++                              mux_5 {
++                                      pins = "gpio66";
++                                      function = "qpic_pad3";
++                                      bias-disable;
++                              };
++
++                              mux_6 {
++                                      pins = "gpio57";
++                                      function = "qpic_pad4";
++                                      bias-disable;
++                              };
++
++                              mux_7 {
++                                      pins = "gpio58";
++                                      function = "qpic_pad5";
++                                      bias-disable;
++                              };
++
++                              mux_8 {
++                                      pins = "gpio59";
++                                      function = "qpic_pad6";
++                                      bias-disable;
++                              };
++
++                              mux_9 {
++                                      pins = "gpio60";
++                                      function = "qpic_pad7";
++                                      bias-disable;
++                              };
++
++                              mux_10 {
++                                      pins = "gpio68";
++                                      function = "qpic_pad8";
++                                      bias-disable;
++                              };
++
++                              pullups {
++                                      pins = "gpio52", "gpio53", "gpio58",
++                                              "gpio59";
++                                      bias-pull-up;
++                              };
++
++                              pulldowns {
++                                      pins = "gpio54", "gpio55", "gpio56",
++                                              "gpio57", "gpio60", "gpio61",
++                                              "gpio62", "gpio63", "gpio64",
++                                              "gpio65", "gpio66", "gpio67",
++                                              "gpio68", "gpio69";
++                                      bias-pull-down;
++                              };
++                      };
+               };
+
+               blsp_dma: dma@7884000 {
+@@ -204,5 +269,15 @@
+               wifi@a800000 {
+                       status = "ok";
+               };
++
++              qpic_bam: dma@7984000 {
++                      status = "ok";
++              };
++
++              nand: qpic-nand@79b0000 {
++                      pinctrl-0 = <&nand_pins>;
++                      pinctrl-names = "default";
++                      status = "ok";
++              };
+       };
+ };
+diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+index 52a64e7..740808b 100644
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -593,5 +593,43 @@
+                                         "legacy";
+                       status = "disabled";
+               };
++
++              qpic_bam: dma@7984000 {
++                      compatible = "qcom,bam-v1.7.0";
++                      reg = <0x7984000 0x1a000>;
++                      interrupts = <0 101 0>;
++                      clocks = <&gcc GCC_QPIC_AHB_CLK>;
++                      clock-names = "bam_clk";
++                      #dma-cells = <1>;
++                      qcom,ee = <0>;
++                      status = "disabled";
++              };
++
++              nand: qpic-nand@79b0000 {
++                      compatible = "qcom,ebi2-nandc-bam", "qcom,msm-nand";
++                      reg = <0x79b0000 0x1000>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      clocks = <&gcc GCC_QPIC_CLK>,
++                              <&gcc GCC_QPIC_AHB_CLK>;
++                      clock-names = "core", "aon";
++
++                      dmas = <&qpic_bam 0>,
++                              <&qpic_bam 1>,
++                              <&qpic_bam 2>;
++                      dma-names = "tx", "rx", "cmd";
++                      status = "disabled";
++
++                      nandcs@0 {
++                              compatible = "qcom,nandcs";
++                              reg = <0>;
++                              #address-cells = <1>;
++                              #size-cells = <1>;
++
++                              nand-ecc-strength = <4>;
++                              nand-ecc-step-size = <512>;
++                              nand-bus-width = <8>;
++                      };
++              };
+       };
+ };
+--
+2.7.2