.has_refsel = true,
};
-static int dsi_init_pll_data(struct platform_device *dsidev)
+static int dsi_init_pll_data(struct dss_device *dss,
+ struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
struct dss_pll *pll = &dsi->pll;
pll->base = dsi->pll_base;
pll->hw = dsi->data->pll_hw;
pll->ops = &dsi_pll_ops;
+ pll->dss = dss;
r = dss_pll_register(pll);
if (r)
static int dsi_bind(struct device *dev, struct device *master, void *data)
{
struct platform_device *dsidev = to_platform_device(dev);
+ struct dss_device *dss = dss_get_device(master);
const struct soc_device_attribute *soc;
const struct dsi_module_id_data *d;
u32 rev;
if (r)
return r;
- dsi_init_pll_data(dsidev);
+ dsi_init_pll_data(dss, dsidev);
pm_runtime_enable(&dsidev->dev);
const char *fclk_name;
unsigned long fclk_rate;
- if (dss_runtime_get())
+ if (dss_runtime_get(&dss))
return;
seq_printf(s, "- DSS -\n");
fclk_name,
fclk_rate);
- dss_runtime_put();
+ dss_runtime_put(&dss);
}
#endif
{
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
- if (dss_runtime_get())
+ if (dss_runtime_get(&dss))
return;
DUMPREG(DSS_REVISION);
DUMPREG(DSS_SDI_STATUS);
}
- dss_runtime_put();
+ dss_runtime_put(&dss);
#undef DUMPREG
}
clk_put(dss.parent_clk);
}
-int dss_runtime_get(void)
+int dss_runtime_get(struct dss_device *dss)
{
int r;
DSSDBG("dss_runtime_get\n");
- r = pm_runtime_get_sync(&dss.pdev->dev);
+ r = pm_runtime_get_sync(&dss->pdev->dev);
WARN_ON(r < 0);
return r < 0 ? r : 0;
}
-void dss_runtime_put(void)
+void dss_runtime_put(struct dss_device *dss)
{
int r;
DSSDBG("dss_runtime_put\n");
- r = pm_runtime_put_sync(&dss.pdev->dev);
+ r = pm_runtime_put_sync(&dss->pdev->dev);
WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
}
+struct dss_device *dss_get_device(struct device *dev)
+{
+ return &dss;
+}
+
/* DEBUGFS */
#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
static void dss_debug_dump_clocks(struct seq_file *s)
}
if (of_property_match_string(np, "reg-names", "pll1") >= 0) {
- dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator);
+ dss.video1_pll = dss_video_pll_init(&dss, pdev, 0,
+ pll_regulator);
if (IS_ERR(dss.video1_pll))
return PTR_ERR(dss.video1_pll);
}
if (of_property_match_string(np, "reg-names", "pll2") >= 0) {
- dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator);
+ dss.video2_pll = dss_video_pll_init(&dss, pdev, 1,
+ pll_regulator);
if (IS_ERR(dss.video2_pll)) {
dss_video_pll_uninit(dss.video1_pll);
return PTR_ERR(dss.video2_pll);
return 0;
}
-static int dss_probe_hardware(void)
+static int dss_probe_hardware(struct dss_device *dss)
{
u32 rev;
int r;
- r = dss_runtime_get();
+ r = dss_runtime_get(dss);
if (r)
return r;
- dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
+ dss->dss_clk_rate = clk_get_rate(dss->dss_clk);
/* Select DPLL */
REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
#endif
- dss.dsi_clk_source[0] = DSS_CLK_SRC_FCK;
- dss.dsi_clk_source[1] = DSS_CLK_SRC_FCK;
- dss.dispc_clk_source = DSS_CLK_SRC_FCK;
- dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK;
- dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK;
+ dss->dsi_clk_source[0] = DSS_CLK_SRC_FCK;
+ dss->dsi_clk_source[1] = DSS_CLK_SRC_FCK;
+ dss->dispc_clk_source = DSS_CLK_SRC_FCK;
+ dss->lcd_clk_source[0] = DSS_CLK_SRC_FCK;
+ dss->lcd_clk_source[1] = DSS_CLK_SRC_FCK;
rev = dss_read_reg(DSS_REVISION);
pr_info("OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
- dss_runtime_put();
+ dss_runtime_put(dss);
return 0;
}
/* Enable runtime PM and probe the hardware. */
pm_runtime_enable(&pdev->dev);
- r = dss_probe_hardware();
+ r = dss_probe_hardware(&dss);
if (r)
goto err_pm_runtime_disable;
struct dss_pll {
const char *name;
enum dss_pll_id id;
+ struct dss_device *dss;
struct clk *clkin;
struct regulator *regulator;
}
#endif /* CONFIG_OMAP2_DSS_DEBUGFS */
-int dss_runtime_get(void);
-void dss_runtime_put(void);
+struct dss_device *dss_get_device(struct device *dev);
+
+int dss_runtime_get(struct dss_device *dss);
+void dss_runtime_put(struct dss_device *dss);
unsigned long dss_get_dispc_clk_rate(void);
unsigned long dss_get_max_fck_rate(void);
const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
/* DSS VIDEO PLL */
-struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
- struct regulator *regulator);
+struct dss_pll *dss_video_pll_init(struct dss_device *dss,
+ struct platform_device *pdev, int id,
+ struct regulator *regulator);
void dss_video_pll_uninit(struct dss_pll *pll);
void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
#include "omapdss.h"
#include "dss.h"
+struct dss_device;
+
/* HDMI Wrapper */
#define HDMI_WP_REVISION 0x0
/* HDMI PLL funcs */
void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
-int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
- struct hdmi_wp_data *wp);
+int hdmi_pll_init(struct dss_device *dss, struct platform_device *pdev,
+ struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
void hdmi_pll_uninit(struct hdmi_pll_data *hpll);
/* HDMI PHY funcs */
static int hdmi4_bind(struct device *dev, struct device *master, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
+ struct dss_device *dss = dss_get_device(master);
int r;
int irq;
if (r)
return r;
- r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
+ r = hdmi_pll_init(dss, pdev, &hdmi.pll, &hdmi.wp);
if (r)
return r;
static int hdmi5_bind(struct device *dev, struct device *master, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
+ struct dss_device *dss = dss_get_device(master);
int r;
int irq;
if (r)
return r;
- r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
+ r = hdmi_pll_init(dss, pdev, &hdmi.pll, &hdmi.wp);
if (r)
return r;
.has_refsel = true,
};
-static int hdmi_init_pll_data(struct platform_device *pdev,
+static int hdmi_init_pll_data(struct dss_device *dss,
+ struct platform_device *pdev,
struct hdmi_pll_data *hpll)
{
struct dss_pll *pll = &hpll->pll;
pll->id = DSS_PLL_HDMI;
pll->base = hpll->base;
pll->clkin = clk;
+ pll->dss = dss;
if (hpll->wp->version == 4)
pll->hw = &dss_omap4_hdmi_pll_hw;
return 0;
}
-int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
- struct hdmi_wp_data *wp)
+int hdmi_pll_init(struct dss_device *dss, struct platform_device *pdev,
+ struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
{
int r;
struct resource *res;
if (IS_ERR(pll->base))
return PTR_ERR(pll->base);
- r = hdmi_init_pll_data(pdev, pll);
+ r = hdmi_init_pll_data(dss, pdev, pll);
if (r) {
DSSERR("failed to init HDMI PLL\n");
return r;
struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
int r;
- r = dss_runtime_get();
+ r = dss_runtime_get(pll->dss);
if (r)
return r;
err_reset:
dss_dpll_disable_scp_clk(vpll);
dss_ctrl_pll_enable(pll->id, false);
- dss_runtime_put();
+ dss_runtime_put(pll->dss);
return r;
}
dss_ctrl_pll_enable(pll->id, false);
- dss_runtime_put();
+ dss_runtime_put(pll->dss);
}
static const struct dss_pll_ops dss_pll_ops = {
.errata_i886 = true,
};
-struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
- struct regulator *regulator)
+struct dss_pll *dss_video_pll_init(struct dss_device *dss,
+ struct platform_device *pdev, int id,
+ struct regulator *regulator)
{
const char * const reg_name[] = { "pll1", "pll2" };
const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" };
pll->base = pll_base;
pll->hw = &dss_dra7_video_pll_hw;
pll->ops = &dss_pll_ops;
+ pll->dss = dss;
r = dss_pll_register(pll);
if (r)