RDMA/hns: Configure mac&gid and user access region for hip08 RoCE driver

In hip08, the user access region(UAR) pfn is calculated
from pci device memory resource.

This patch mainly sets mac and gid table by configuring
the relevant registers and updates the uar pfn for hip08 SoC.

Signed-off-by: Lijun Ou <oulijun@huawei.com>
Signed-off-by: Shaobo Xu <xushaobo2@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>

diff --git a/drivers/infiniband/hw/hns/hns_roce_common.h b/drivers/infiniband/hw/hns/hns_roce_common.h
index 0c950f8e4249a30a241fc206194fbb2c4b000bf1..7ecb7a4147a8bbd0cd9f86e6945d8774c1739a41 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_common.h
+++ b/drivers/infiniband/hw/hns/hns_roce_common.h
@@ -376,4 +376,13 @@
 #define ROCEE_RX_CMQ_TAIL_REG                  0x07024
 #define ROCEE_RX_CMQ_HEAD_REG                  0x07028
 
+#define ROCEE_VF_SMAC_CFG0_REG                 0x12000
+#define ROCEE_VF_SMAC_CFG1_REG                 0x12004
+
+#define ROCEE_VF_SGID_CFG0_REG                 0x10000
+#define ROCEE_VF_SGID_CFG1_REG                 0x10004
+#define ROCEE_VF_SGID_CFG2_REG                 0x10008
+#define ROCEE_VF_SGID_CFG3_REG                 0x1000c
+#define ROCEE_VF_SGID_CFG4_REG                 0x10010
+
 #endif /* _HNS_ROCE_COMMON_H */

diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index 542540db45beb553cab72f50d24ff00c95e7a87d..e7aeb531b7a0b511f2928a3b4d4235e1bf97aa46 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -718,6 +718,53 @@ static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
        return 0;
 }
 
+static void hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
+                               int gid_index, union ib_gid *gid)
+{
+       u32 *p;
+       u32 val;
+
+       p = (u32 *)&gid->raw[0];
+       roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG0_REG +
+                      0x20 * gid_index);
+
+       p = (u32 *)&gid->raw[4];
+       roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG1_REG +
+                      0x20 * gid_index);
+
+       p = (u32 *)&gid->raw[8];
+       roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG2_REG +
+                      0x20 * gid_index);
+
+       p = (u32 *)&gid->raw[0xc];
+       roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG3_REG +
+                      0x20 * gid_index);
+
+       val = roce_read(hr_dev, ROCEE_VF_SGID_CFG4_REG + 0x20 * gid_index);
+       roce_set_field(val, ROCEE_VF_SGID_CFG4_SGID_TYPE_M,
+                      ROCEE_VF_SGID_CFG4_SGID_TYPE_S, 0);
+
+       roce_write(hr_dev, ROCEE_VF_SGID_CFG4_REG + 0x20 * gid_index, val);
+}
+
+static void hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
+                               u8 *addr)
+{
+       u16 reg_smac_h;
+       u32 reg_smac_l;
+       u32 val;
+
+       reg_smac_l = *(u32 *)(&addr[0]);
+       roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_VF_SMAC_CFG0_REG +
+                      0x08 * phy_port);
+       val = roce_read(hr_dev, ROCEE_VF_SMAC_CFG1_REG + 0x08 * phy_port);
+
+       reg_smac_h  = *(u16 *)(&addr[4]);
+       roce_set_field(val, ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M,
+                      ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S, reg_smac_h);
+       roce_write(hr_dev, ROCEE_VF_SMAC_CFG1_REG + 0x08 * phy_port, val);
+}
+
 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
                               struct hns_roce_hem_table *table, int obj,
                               int step_idx)
@@ -857,6 +904,8 @@ static const struct hns_roce_hw hns_roce_hw_v2 = {
        .hw_profile = hns_roce_v2_profile,
        .post_mbox = hns_roce_v2_post_mbox,
        .chk_mbox = hns_roce_v2_chk_mbox,
+       .set_gid = hns_roce_v2_set_gid,
+       .set_mac = hns_roce_v2_set_mac,
        .set_hem = hns_roce_v2_set_hem,
        .clear_hem = hns_roce_v2_clear_hem,
 };

diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
index 593d886943f19f5bb3dd8ea81c896e2560ecdf3e..aee8f34be1a1b95cdeb4a864610292462f6d168b 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
@@ -246,6 +246,13 @@ struct hns_roce_vf_res_b {
 #define VF_RES_B_DATA_3_VF_SL_NUM_S 16
 #define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16)
 
+/* Reg field definition */
+#define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S 0
+#define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M GENMASK(15, 0)
+
+#define ROCEE_VF_SGID_CFG4_SGID_TYPE_S 0
+#define ROCEE_VF_SGID_CFG4_SGID_TYPE_M GENMASK(1, 0)
+
 struct hns_roce_cfg_bt_attr {
        u32 vf_qpc_cfg;
        u32 vf_srqc_cfg;

diff --git a/drivers/infiniband/hw/hns/hns_roce_pd.c b/drivers/infiniband/hw/hns/hns_roce_pd.c
index 079bb10237cf9fd4680b7377fab79ced6d2695f2..bdab2188c04a9ab6277dcb84cb231be5b6388c90 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_pd.c
+++ b/drivers/infiniband/hw/hns/hns_roce_pd.c
@@ -31,6 +31,7 @@
  */
 
 #include <linux/platform_device.h>
+#include <linux/pci.h>
 #include "hns_roce_device.h"
 
 static int hns_roce_pd_alloc(struct hns_roce_dev *hr_dev, unsigned long *pdn)
@@ -111,12 +112,17 @@ int hns_roce_uar_alloc(struct hns_roce_dev *hr_dev, struct hns_roce_uar *uar)
                uar->index = (uar->index - 1) %
                             (hr_dev->caps.phy_num_uars - 1) + 1;
 
-       res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
-       if (!res) {
-               dev_err(&hr_dev->pdev->dev, "memory resource not found!\n");
-               return -EINVAL;
+       if (!dev_is_pci(hr_dev->dev)) {
+               res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
+               if (!res) {
+                       dev_err(&hr_dev->pdev->dev, "memory resource not found!\n");
+                       return -EINVAL;
+               }
+               uar->pfn = ((res->start) >> PAGE_SHIFT) + uar->index;
+       } else {
+               uar->pfn = ((pci_resource_start(hr_dev->pci_dev, 2))
+                          >> PAGE_SHIFT);
        }
-       uar->pfn = ((res->start) >> PAGE_SHIFT) + uar->index;
 
        return 0;
 }