#include <debug.h>
#include <delay_timer.h>
#include <dw_mmc.h>
-#include <emmc.h>
#include <errno.h>
+#include <mmc.h>
#include <mmio.h>
#include <string.h>
#define DWMMC_8BIT_MODE (1 << 6)
+#define DWMMC_ADDRESS_MASK U(0x0f)
+
#define TIMEOUT 100000
struct dw_idmac_desc {
};
static void dw_init(void);
-static int dw_send_cmd(emmc_cmd_t *cmd);
-static int dw_set_ios(int clk, int width);
+static int dw_send_cmd(struct mmc_cmd *cmd);
+static int dw_set_ios(unsigned int clk, unsigned int width);
static int dw_prepare(int lba, uintptr_t buf, size_t size);
static int dw_read(int lba, uintptr_t buf, size_t size);
static int dw_write(int lba, uintptr_t buf, size_t size);
-static const emmc_ops_t dw_mmc_ops = {
+static const struct mmc_ops dw_mmc_ops = {
.init = dw_init,
.send_cmd = dw_send_cmd,
.set_ios = dw_set_ios,
unsigned int data;
uintptr_t base;
- assert((dw_params.reg_base & EMMC_BLOCK_MASK) == 0);
+ assert((dw_params.reg_base & MMC_BLOCK_MASK) == 0);
base = dw_params.reg_base;
mmio_write_32(base + DWMMC_PWREN, 1);
mmio_write_32(base + DWMMC_INTMASK, 0);
mmio_write_32(base + DWMMC_TMOUT, ~0);
mmio_write_32(base + DWMMC_IDINTEN, ~0);
- mmio_write_32(base + DWMMC_BLKSIZ, EMMC_BLOCK_SIZE);
+ mmio_write_32(base + DWMMC_BLKSIZ, MMC_BLOCK_SIZE);
mmio_write_32(base + DWMMC_BYTCNT, 256 * 1024);
mmio_write_32(base + DWMMC_DEBNCE, 0x00ffffff);
mmio_write_32(base + DWMMC_BMOD, BMOD_SWRESET);
mmio_write_32(base + DWMMC_BMOD, data);
udelay(100);
- dw_set_clk(EMMC_BOOT_CLK_RATE);
+ dw_set_clk(MMC_BOOT_CLK_RATE);
udelay(100);
}
-static int dw_send_cmd(emmc_cmd_t *cmd)
+static int dw_send_cmd(struct mmc_cmd *cmd)
{
unsigned int op, data, err_mask;
uintptr_t base;
base = dw_params.reg_base;
switch (cmd->cmd_idx) {
- case EMMC_CMD0:
+ case 0:
op = CMD_SEND_INIT;
break;
- case EMMC_CMD12:
+ case 12:
op = CMD_STOP_ABORT_CMD;
break;
- case EMMC_CMD13:
+ case 13:
op = CMD_WAIT_PRVDATA_COMPLETE;
break;
- case EMMC_CMD8:
- case EMMC_CMD17:
- case EMMC_CMD18:
+ case 8:
+ case 17:
+ case 18:
op = CMD_DATA_TRANS_EXPECT | CMD_WAIT_PRVDATA_COMPLETE;
break;
- case EMMC_CMD24:
- case EMMC_CMD25:
+ case 24:
+ case 25:
op = CMD_WRITE | CMD_DATA_TRANS_EXPECT |
CMD_WAIT_PRVDATA_COMPLETE;
break;
switch (cmd->resp_type) {
case 0:
break;
- case EMMC_RESPONSE_R2:
+ case MMC_RESPONSE_R(2):
op |= CMD_RESP_EXPECT | CMD_CHECK_RESP_CRC |
CMD_RESP_LEN;
break;
- case EMMC_RESPONSE_R3:
+ case MMC_RESPONSE_R(3):
op |= CMD_RESP_EXPECT;
break;
default:
return 0;
}
-static int dw_set_ios(int clk, int width)
+static int dw_set_ios(unsigned int clk, unsigned int width)
{
switch (width) {
- case EMMC_BUS_WIDTH_1:
+ case MMC_BUS_WIDTH_1:
mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_1BIT);
break;
- case EMMC_BUS_WIDTH_4:
+ case MMC_BUS_WIDTH_4:
mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_4BIT);
break;
- case EMMC_BUS_WIDTH_8:
+ case MMC_BUS_WIDTH_8:
mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_8BIT);
break;
default:
int desc_cnt, i, last;
uintptr_t base;
- assert(((buf & EMMC_BLOCK_MASK) == 0) &&
- ((size % EMMC_BLOCK_SIZE) == 0) &&
+ assert(((buf & DWMMC_ADDRESS_MASK) == 0) &&
+ ((size % MMC_BLOCK_SIZE) == 0) &&
(dw_params.desc_size > 0) &&
- ((dw_params.reg_base & EMMC_BLOCK_MASK) == 0) &&
- ((dw_params.desc_base & EMMC_BLOCK_MASK) == 0) &&
- ((dw_params.desc_size & EMMC_BLOCK_MASK) == 0));
+ ((dw_params.reg_base & MMC_BLOCK_MASK) == 0) &&
+ ((dw_params.desc_base & MMC_BLOCK_MASK) == 0) &&
+ ((dw_params.desc_size & MMC_BLOCK_MASK) == 0));
+
+ flush_dcache_range(buf, size);
desc_cnt = (size + DWMMC_DMA_MAX_BUFFER_SIZE - 1) /
DWMMC_DMA_MAX_BUFFER_SIZE;
(desc + last)->des3 = 0;
mmio_write_32(base + DWMMC_DBADDR, dw_params.desc_base);
- clean_dcache_range(dw_params.desc_base,
+ flush_dcache_range(dw_params.desc_base,
desc_cnt * DWMMC_DMA_MAX_BUFFER_SIZE);
return 0;
return 0;
}
-void dw_mmc_init(dw_mmc_params_t *params)
+void dw_mmc_init(dw_mmc_params_t *params, struct mmc_device_info *info)
{
assert((params != 0) &&
- ((params->reg_base & EMMC_BLOCK_MASK) == 0) &&
- ((params->desc_base & EMMC_BLOCK_MASK) == 0) &&
- ((params->desc_size & EMMC_BLOCK_MASK) == 0) &&
+ ((params->reg_base & MMC_BLOCK_MASK) == 0) &&
+ ((params->desc_base & MMC_BLOCK_MASK) == 0) &&
+ ((params->desc_size & MMC_BLOCK_MASK) == 0) &&
(params->desc_size > 0) &&
(params->clk_rate > 0) &&
- ((params->bus_width == EMMC_BUS_WIDTH_1) ||
- (params->bus_width == EMMC_BUS_WIDTH_4) ||
- (params->bus_width == EMMC_BUS_WIDTH_8)));
+ ((params->bus_width == MMC_BUS_WIDTH_1) ||
+ (params->bus_width == MMC_BUS_WIDTH_4) ||
+ (params->bus_width == MMC_BUS_WIDTH_8)));
memcpy(&dw_params, params, sizeof(dw_mmc_params_t));
- emmc_init(&dw_mmc_ops, params->clk_rate, params->bus_width,
- params->flags);
+ mmc_init(&dw_mmc_ops, params->clk_rate, params->bus_width,
+ params->flags, info);
}