net: dsa: qca8k: Force CPU port to its highest bandwidth

By default autonegotiation is enabled to configure MAC on all ports.
For the CPU port autonegotiation can not be used so we need to set
some sensible defaults manually.

This patch forces the default setting of the CPU port to 1000Mbps/full
duplex which is the chip maximum capability.

Also correct size of the bit field used to configure link speed.

Fixes: 6b93fb46480a ("net-next: dsa: add new driver for qca8xxx family")
Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index a32744e40baf01d0a8d6501e4a41dc3c3c03c3f5..0d7e71528be59fd296a6de9e390cb5cc46342752 100644 (file)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -490,6 +490,7 @@ qca8k_setup(struct dsa_switch *ds)
 {
        struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
        int ret, i, phy_mode = -1;
+       u32 mask;
 
        /* Make sure that port 0 is the cpu port */
        if (!dsa_is_cpu_port(ds, 0)) {
@@ -515,7 +516,10 @@ qca8k_setup(struct dsa_switch *ds)
        if (ret < 0)
                return ret;
 
-       /* Enable CPU Port */
+       /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
+       mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW |
+              QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
+       qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
        qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
                      QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
        qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);

diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index 1cf8a920d4ffc5ed84b8fd0948fa088b2b3ebf1b..5bda16555478bb39cf1a4858f041a18a7722c5a2 100644 (file)
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -51,8 +51,10 @@
 #define QCA8K_GOL_MAC_ADDR0                            0x60
 #define QCA8K_GOL_MAC_ADDR1                            0x64
 #define QCA8K_REG_PORT_STATUS(_i)                      (0x07c + (_i) * 4)
-#define   QCA8K_PORT_STATUS_SPEED                      GENMASK(2, 0)
-#define   QCA8K_PORT_STATUS_SPEED_S                    0
+#define   QCA8K_PORT_STATUS_SPEED                      GENMASK(1, 0)
+#define   QCA8K_PORT_STATUS_SPEED_10                   0
+#define   QCA8K_PORT_STATUS_SPEED_100                  0x1
+#define   QCA8K_PORT_STATUS_SPEED_1000                 0x2
 #define   QCA8K_PORT_STATUS_TXMAC                      BIT(2)
 #define   QCA8K_PORT_STATUS_RXMAC                      BIT(3)
 #define   QCA8K_PORT_STATUS_TXFLOW                     BIT(4)