Access system registers directly in assembler

Instead of using the system register helper functions to read
or write system registers, assembler coded functions should
use MRS/MSR instructions. This results in faster and more
compact code.

This change replaces all usage of the helper functions with
direct register accesses.

Change-Id: I791d5f11f257010bb3e6a72c6c5ab8779f1982b3

diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S
index e25386f74d7996ca4eacea00b223a3c2683a3c3f..c081af48feada0636e0ab6d6b7b8137f8e7a72f6 100644 (file)
--- a/bl1/aarch64/bl1_entrypoint.S
+++ b/bl1/aarch64/bl1_entrypoint.S
@@ -97,10 +97,10 @@ _wait_for_entrypoint:
         * their turn to be woken up
         * ---------------------------------------------
         */
-       bl      read_mpidr
+       mrs     x0, mpidr_el1
        bl      platform_get_entrypoint
        cbnz    x0, _do_warm_boot
-       bl      read_mpidr
+       mrs     x0, mpidr_el1
        bl      platform_is_primary_cpu
        cbnz    x0, _do_cold_boot
 

diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S
index 71fd4cd75a558189626def4708332199a496ad56..a87b20f5c8d3e57f48a79a24132eb1c2a0b8e056 100644 (file)
--- a/bl1/aarch64/bl1_exceptions.S
+++ b/bl1/aarch64/bl1_exceptions.S
@@ -189,7 +189,7 @@ func process_exception
        mov     x0, #SYNC_EXCEPTION_AARCH64
        bl      plat_report_exception
 
-       bl      read_esr_el3
+       mrs     x0, esr_el3
        ubfx    x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
        cmp     x1, #EC_AARCH64_SMC
        b.ne    panic
@@ -201,10 +201,8 @@ func process_exception
        mov     x2, x3
        mov     x3, x4
        bl      display_boot_progress
-       mov     x0, x20
-       bl      write_elr
-       mov     x0, x21
-       bl      write_spsr
+       msr     elr_el3, x20
+       msr     spsr_el3, x21
        ubfx    x0, x21, #MODE_EL_SHIFT, #2
        cmp     x0, #MODE_EL3
        b.ne    skip_mmu_teardown
@@ -216,7 +214,7 @@ func process_exception
         * ---------------------------------------------
         */
        bl      disable_mmu_icache_el3
-       bl      tlbialle3
+       tlbi    alle3
 skip_mmu_teardown:
        ldp     x6, x7, [sp, #0x30]
        ldp     x4, x5, [sp, #0x20]

diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S
index cd07aa9defaf49b883902c9b7b54026ab13ec8c3..4f7565f41e5589a9de4e671dc622fd80b4b79bde 100644 (file)
--- a/bl2/aarch64/bl2_entrypoint.S
+++ b/bl2/aarch64/bl2_entrypoint.S
@@ -54,8 +54,7 @@ func bl2_entrypoint
         * So, make sure no secondary has lost its way.
         * ---------------------------------------------
         */
-       bl      read_mpidr
-       mov     x19, x0
+       mrs     x0, mpidr_el1
        bl      platform_is_primary_cpu
        cbz     x0, _panic
 
@@ -102,7 +101,7 @@ func bl2_entrypoint
         * ease the pain of initializing the MMU
         * --------------------------------------------
         */
-       mov     x0, x19
+       mrs     x0, mpidr_el1
        bl      platform_set_coherent_stack
 
        /* ---------------------------------------------
@@ -120,7 +119,7 @@ func bl2_entrypoint
         * -IS-WBWA memory
         * ---------------------------------------------
         */
-       mov     x0, x19
+       mrs     x0, mpidr_el1
        bl      platform_set_stack
 
        /* ---------------------------------------------

diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index 1b79421df57e5f52b0e6d9d2e06d4f750cf2831e..13bd5b897ca6c86146a68eb1fae2e919fd727402 100644 (file)
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -107,8 +107,7 @@ func bl31_entrypoint
         * So, make sure no secondary has lost its way.
         * ---------------------------------------------
         */
-       bl      read_mpidr
-       mov     x19, x0
+       mrs     x0, mpidr_el1
        bl      platform_is_primary_cpu
        cbz     x0, _panic
 
@@ -137,7 +136,7 @@ func bl31_entrypoint
         * ease the pain of initializing the MMU
         * --------------------------------------------
         */
-       mov     x0, x19
+       mrs     x0, mpidr_el1
        bl      platform_set_coherent_stack
 
        /* ---------------------------------------------
@@ -154,7 +153,7 @@ func bl31_entrypoint
         * -IS-WBWA memory
         * ---------------------------------------------
         */
-       mov     x0, x19
+       mrs     x0, mpidr_el1
        bl      platform_set_stack
 
        /* ---------------------------------------------

diff --git a/include/common/asm_macros.S b/include/common/asm_macros.S
index 6cf1a19f7a59628c6189c12b543db5f94d06e6f2..a41b7297023297997350fb8b3c6157053902505e 100644 (file)
--- a/include/common/asm_macros.S
+++ b/include/common/asm_macros.S
@@ -58,7 +58,7 @@
 
 
        .macro  smc_check  label
-       bl      read_esr
+       mrs     x0, esr_el3
        ubfx    x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
        cmp     x0, #EC_AARCH64_SMC
        b.ne    $label

diff --git a/lib/aarch64/cpu_helpers.S b/lib/aarch64/cpu_helpers.S
index 4e5eb5bd93ea5fc55d09f331eea310ecbc972abc..abb996d69b0ac632f535a086788fe3ac72c03ebf 100644 (file)
--- a/lib/aarch64/cpu_helpers.S
+++ b/lib/aarch64/cpu_helpers.S
@@ -35,13 +35,11 @@
 
 
 func cpu_reset_handler
-       mov     x19, x30 // lr
-
        /* ---------------------------------------------
         * As a bare minimal enable the SMP bit.
         * ---------------------------------------------
         */
-       bl      read_midr
+       mrs     x0, midr_el1
        lsr     x0, x0, #MIDR_PN_SHIFT
        and     x0, x0, #MIDR_PN_MASK
        cmp     x0, #MIDR_PN_A57
@@ -49,9 +47,9 @@ func cpu_reset_handler
        cmp     x0, #MIDR_PN_A53
        b.ne    smp_setup_end
 smp_setup_begin:
-       bl      read_cpuectlr
+       mrs     x0, CPUECTLR_EL1
        orr     x0, x0, #CPUECTLR_SMP_BIT
-       bl      write_cpuectlr
+       msr     CPUECTLR_EL1, x0
        isb
 smp_setup_end:
-       ret     x19
+       ret

diff --git a/plat/fvp/aarch64/bl1_plat_helpers.S b/plat/fvp/aarch64/bl1_plat_helpers.S
index 92075ea4cc78eb1f6353c766802d96e5ea0e96e8..b4d44586d2e51b648e785715a03f8b46d1a1ed7a 100644 (file)
--- a/plat/fvp/aarch64/bl1_plat_helpers.S
+++ b/plat/fvp/aarch64/bl1_plat_helpers.S
@@ -67,7 +67,7 @@ func plat_secondary_cold_boot_setup
         * loader zeroes out the zi section.
         * ---------------------------------------------
         */
-       bl      read_mpidr
+       mrs     x0, mpidr_el1
        ldr     x1, =PWRC_BASE
        str     w0, [x1, #PPOFFR_OFF]
 
@@ -173,8 +173,6 @@ func platform_mem_init
 func platform_cold_boot_init
        mov     x20, x0
        bl      platform_mem_init
-       bl      read_mpidr
-       mov     x19, x0
 
        /* ---------------------------------------------
         * Give ourselves a small coherent stack to
@@ -182,6 +180,7 @@ func platform_cold_boot_init
         * CCI in assembler
         * ---------------------------------------------
         */
+       mrs     x0, mpidr_el1
        bl      platform_set_coherent_stack
 
        /* ---------------------------------------------
@@ -200,7 +199,7 @@ func platform_cold_boot_init
         * -IS-WBWA memory
         * ---------------------------------------------
         */
-       mov     x0, x19
+       mrs     x0, mpidr_el1
        bl      platform_set_stack
 
        /* ---------------------------------------------

diff --git a/services/std_svc/psci/psci_entry.S b/services/std_svc/psci/psci_entry.S
index ec55a8190b97a3f67c779b0634b0663737b4b860..25adaa11e92a7cec6d118fe157b927987ca6874c 100644 (file)
--- a/services/std_svc/psci/psci_entry.S
+++ b/services/std_svc/psci/psci_entry.S
@@ -76,8 +76,7 @@ psci_aff_common_finish_entry:
         */
        msr     spsel, #0
 
-       bl      read_mpidr
-       mov     x19, x0
+       mrs     x0, mpidr_el1
        bl      platform_set_coherent_stack
 
        /* ---------------------------------------------
@@ -85,14 +84,14 @@ psci_aff_common_finish_entry:
         * level 0.
         * ---------------------------------------------
         */
-       mov     x0, x19
+       mrs     x0, mpidr_el1
        bl      get_power_on_target_afflvl
        cmp     x0, xzr
        b.lt    _panic
        mov     x3, x23
        mov     x2, x0
-       mov     x0, x19
        mov     x1, #MPIDR_AFFLVL0
+       mrs     x0, mpidr_el1
        blr     x22
 
        /* --------------------------------------------
@@ -100,7 +99,7 @@ psci_aff_common_finish_entry:
         * -IS-WBWA memory
         * --------------------------------------------
         */
-       mov     x0, x19
+       mrs     x0, mpidr_el1
        bl      platform_set_stack
 
        zero_callee_saved_regs
@@ -119,7 +118,7 @@ func __psci_cpu_off
        sub     sp, sp, #0x10
        stp     x19, x20, [sp, #0]
        mov     x19, sp
-       bl      read_mpidr
+       mrs     x0, mpidr_el1
        bl      platform_set_coherent_stack
        bl      psci_cpu_off
        mov     x1, #PSCI_E_SUCCESS
@@ -140,7 +139,7 @@ func __psci_cpu_suspend
        mov     x20, x0
        mov     x21, x1
        mov     x22, x2
-       bl      read_mpidr
+       mrs     x0, mpidr_el1
        bl      platform_set_coherent_stack
        mov     x0, x20
        mov     x1, x21