Introducing support for Cortex-A65AE

Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422
Signed-off-by: Imre Kis <imre.kis@arm.com>

diff --git a/include/lib/cpus/aarch64/cortex_a65ae.h b/include/lib/cpus/aarch64/cortex_a65ae.h
new file mode 100644 (file)
index 0000000..bd4a881
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a65ae.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A65AE_H
+#define CORTEX_A65AE_H
+
+#include <lib/utils_def.h>
+
+#define CORTEX_A65AE_MIDR                      U(0x410FD430)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A65AE_ECTLR_EL1         S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A65AE_CPUACTLR_EL1      S3_0_C15_C1_0
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+
+#define CORTEX_A65AE_CPUPWRCTLR_EL1    S3_0_C15_C2_7
+#define CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT     (U(1) << 0)
+
+#endif /* CORTEX_A65AE_H */

diff --git a/lib/cpus/aarch64/cortex_a65ae.S b/lib/cpus/aarch64/cortex_a65ae.S
new file mode 100644 (file)
index 0000000..ac6583e
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a65ae.S
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <cortex_a65ae.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if !HW_ASSISTED_COHERENCY
+#error "Cortex-A65AE must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS
+#error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+/* -------------------------------------------------
+ * The CPU Ops reset function for Cortex-A65.
+ * Shall clobber: x0-x19
+ * -------------------------------------------------
+ */
+func cortex_a65ae_reset_func
+       mov     x19, x30
+
+#if ERRATA_DSU_936184
+       bl      errata_dsu_936184_wa
+#endif
+
+       ret     x19
+endfunc cortex_a65ae_reset_func
+
+func cortex_a65ae_cpu_pwr_dwn
+       mrs     x0, CORTEX_A65AE_CPUPWRCTLR_EL1
+       orr     x0, x0, #CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+       msr     CORTEX_A65AE_CPUPWRCTLR_EL1, x0
+       isb
+       ret
+endfunc cortex_a65ae_cpu_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex-A65AE. Must follow AAPCS.
+ */
+func cortex_a65ae_errata_report
+       stp     x8, x30, [sp, #-16]!
+
+       bl      cpu_get_rev_var
+       mov     x8, x0
+
+       /*
+        * Report all errata. The revision-variant information is passed to
+        * checking functions of each errata.
+        */
+       report_errata ERRATA_DSU_936184, cortex_a65ae, dsu_936184
+
+       ldp     x8, x30, [sp], #16
+       ret
+endfunc cortex_a65ae_errata_report
+#endif
+
+.section .rodata.cortex_a65ae_regs, "aS"
+cortex_a65ae_regs:  /* The ascii list of register names to be reported */
+       .asciz  "cpuectlr_el1", ""
+
+func cortex_a65ae_cpu_reg_dump
+       adr     x6, cortex_a65ae_regs
+       mrs     x8, CORTEX_A65AE_ECTLR_EL1
+       ret
+endfunc cortex_a65ae_cpu_reg_dump
+
+declare_cpu_ops cortex_a65ae, CORTEX_A65AE_MIDR, \
+       cortex_a65ae_reset_func, \
+       cortex_a65ae_cpu_pwr_dwn

diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index c8e2169c32b07b080fb0d93ee455ca2b1dc01b73..317f0bada0297e1088ca156f920213e871ce3bd0 100644 (file)
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -117,7 +117,8 @@ else
                                        lib/cpus/aarch64/neoverse_zeus.S        \
                                        lib/cpus/aarch64/cortex_hercules.S      \
                                        lib/cpus/aarch64/cortex_hercules_ae.S   \
-                                       lib/cpus/aarch64/cortex_a65.S
+                                       lib/cpus/aarch64/cortex_a65.S           \
+                                       lib/cpus/aarch64/cortex_a65ae.S
        endif
        # AArch64/AArch32 cores
        FVP_CPU_LIBS    +=      lib/cpus/aarch64/cortex_a55.S           \