ASoC: tlv320aic32x4: Use correct shift definition for DATALEN bits

Setting the DATALEN bit field requires shifting our value by 4. Setting
the OSR value of the PLL divider also requires a shift by 4. Currently
the code abuses this fact and uses the shift for the divider register to
set the data-length register. Fix this here by using the definition meant
for this register.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c
index 8f9719e6cdfd4fba45b9200cfdf65b1741f02434..9f643199e1ba66fef9fb3c92a054217fc0822f67 100644 (file)
--- a/sound/soc/codecs/tlv320aic32x4.c
+++ b/sound/soc/codecs/tlv320aic32x4.c
@@ -738,15 +738,20 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
        data = data & ~(3 << 4);
        switch (params_width(params)) {
        case 16:
+               data |= (AIC32X4_WORD_LEN_16BITS <<
+                        AIC32X4_IFACE1_DATALEN_SHIFT);
                break;
        case 20:
-               data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
+               data |= (AIC32X4_WORD_LEN_20BITS <<
+                        AIC32X4_IFACE1_DATALEN_SHIFT);
                break;
        case 24:
-               data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
+               data |= (AIC32X4_WORD_LEN_24BITS <<
+                        AIC32X4_IFACE1_DATALEN_SHIFT);
                break;
        case 32:
-               data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
+               data |= (AIC32X4_WORD_LEN_32BITS <<
+                        AIC32X4_IFACE1_DATALEN_SHIFT);
                break;
        }
        snd_soc_write(codec, AIC32X4_IFACE1, data);