gr->func->init_419cc0(gr);
if (gr->func->init_419eb4)
gr->func->init_419eb4(gr);
+ if (gr->func->init_419c9c)
+ gr->func->init_419c9c(gr);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
void (*init_sked_hww_esr)(struct gf100_gr *);
void (*init_419cc0)(struct gf100_gr *);
void (*init_419eb4)(struct gf100_gr *);
+ void (*init_419c9c)(struct gf100_gr *);
void (*init_ppc_exceptions)(struct gf100_gr *);
void (*set_hww_esr_report_mask)(struct gf100_gr *);
const struct gf100_gr_pack *mmio;
* PGRAPH engine/subdev functions
******************************************************************************/
+static void
+gp100_gr_init_419c9c(struct gf100_gr *gr)
+{
+ struct nvkm_device *device = gr->base.engine.subdev.device;
+ nvkm_mask(device, 0x419c9c, 0x00010000, 0x00010000);
+ nvkm_mask(device, 0x419c9c, 0x00020000, 0x00020000);
+}
+
void
gp100_gr_init_fecs_exceptions(struct gf100_gr *gr)
{
nvkm_wr32(device, 0x405840, 0xc0000000);
nvkm_wr32(device, 0x405844, 0x00ffffff);
gr->func->init_419cc0(gr);
-
- nvkm_mask(device, 0x419c9c, 0x00010000, 0x00010000);
- nvkm_mask(device, 0x419c9c, 0x00020000, 0x00020000);
+ if (gr->func->init_419c9c)
+ gr->func->init_419c9c(gr);
gr->func->init_ppc_exceptions(gr);
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_419cc0 = gf100_gr_init_419cc0,
+ .init_419c9c = gp100_gr_init_419c9c,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.rops = gm200_gr_rops,
.ppc_nr = 2,