lantiq: move patch to proper folder

Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 38884

diff --git a/linux/lantiq/patches-3.10/0200-NET-fix-etop-registers.patch b/linux/lantiq/patches-3.10/0200-NET-fix-etop-registers.patch
deleted file mode 100644 (file)
index 8502cf3..0000000
--- a/linux/lantiq/patches-3.10/0200-NET-fix-etop-registers.patch
+++ /dev/null
@@ -1,121 +0,0 @@
---- a/drivers/net/ethernet/lantiq_etop.c
-+++ b/drivers/net/ethernet/lantiq_etop.c
-@@ -47,7 +47,7 @@
- #include <xway_dma.h>
- #include <lantiq_platform.h>
- 
--#define LTQ_ETOP_MDIO         0x11804
-+#define LTQ_ETOP_MDIO_ACC     0x11804
- #define MDIO_REQUEST          0x80000000
- #define MDIO_READ             0x40000000
- #define MDIO_ADDR_MASK                0x1f
-@@ -56,27 +56,38 @@
- #define MDIO_REG_OFFSET               0x10
- #define MDIO_VAL_MASK         0xffff
- 
--#define PPE32_CGEN            0x800
--#define LQ_PPE32_ENET_MAC_CFG 0x1840
-+#define LTQ_ETOP_MDIO_CFG       0x11800
-+#define MDIO_CFG_MASK           0x6
-+
-+#define LTQ_ETOP_CFG            0x11808
-+#define LTQ_ETOP_IGPLEN         0x11820
-+#define LTQ_ETOP_MAC_CFG      0x11840
- 
- #define LTQ_ETOP_ENETS0               0x11850
- #define LTQ_ETOP_MAC_DA0      0x1186C
- #define LTQ_ETOP_MAC_DA1      0x11870
--#define LTQ_ETOP_CFG          0x16020
--#define LTQ_ETOP_IGPLEN               0x16080
-+
-+#define MAC_CFG_MASK          0xfff
-+#define MAC_CFG_CGEN          (1 << 11)
-+#define MAC_CFG_DUPLEX                (1 << 2)
-+#define MAC_CFG_SPEED         (1 << 1)
-+#define MAC_CFG_LINK          (1 << 0)
- 
- #define MAX_DMA_CHAN          0x8
- #define MAX_DMA_CRC_LEN               0x4
- #define MAX_DMA_DATA_LEN      0x600
- 
- #define ETOP_FTCU             BIT(28)
--#define ETOP_MII_MASK         0xf
--#define ETOP_MII_NORMAL               0xd
--#define ETOP_MII_REVERSE      0xe
- #define ETOP_PLEN_UNDER               0x40
--#define ETOP_CGEN             0x800
- #define ETOP_CFG_MII0         0x01
- 
-+#define ETOP_CFG_MASK           0xfff
-+#define ETOP_CFG_FEN0         (1 << 8)
-+#define ETOP_CFG_SEN0         (1 << 6)
-+#define ETOP_CFG_OFF1         (1 << 3)
-+#define ETOP_CFG_REMII0               (1 << 1)
-+#define ETOP_CFG_OFF0         (1 << 0)
-+
- #define LTQ_GBIT_MDIO_CTL     0xCC
- #define LTQ_GBIT_MDIO_DATA    0xd0
- #define LTQ_GBIT_GCTL0                0x68
-@@ -355,16 +366,19 @@ ltq_etop_hw_init(struct net_device *dev)
-               /* force the etops link to the gbit to MII */
-               mii_mode = PHY_INTERFACE_MODE_MII;
-       }
-+      ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
-+      ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
-+                      MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
- 
-       switch (mii_mode) {
-       case PHY_INTERFACE_MODE_RMII:
--              ltq_etop_w32_mask(ETOP_MII_MASK,
--                      ETOP_MII_REVERSE, LTQ_ETOP_CFG);
-+              ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
-+                      ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
-               break;
- 
-       case PHY_INTERFACE_MODE_MII:
--              ltq_etop_w32_mask(ETOP_MII_MASK,
--                      ETOP_MII_NORMAL, LTQ_ETOP_CFG);
-+              ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
-+                      ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
-               break;
- 
-       default:
-@@ -385,9 +399,6 @@ ltq_etop_hw_init(struct net_device *dev)
-               return -ENOTSUPP;
-       }
- 
--      /* enable crc generation */
--      ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
--
-       return 0;
- }
- 
-@@ -521,9 +532,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
-               ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
-               phy_data;
- 
--      while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
-+      while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
-               ;
--      ltq_etop_w32(val, LTQ_ETOP_MDIO);
-+      ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
-       return 0;
- }
- 
-@@ -534,12 +545,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
-               ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
-               ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
- 
--      while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
-+      while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
-               ;
--      ltq_etop_w32(val, LTQ_ETOP_MDIO);
--      while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
-+      ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
-+      while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
-               ;
--      val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
-+      val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
-       return val;
- }
- 

diff --git a/target/linux/lantiq/patches-3.10/0200-NET-fix-etop-registers.patch b/target/linux/lantiq/patches-3.10/0200-NET-fix-etop-registers.patch
new file mode 100644 (file)
index 0000000..8502cf3
--- /dev/null
+++ b/target/linux/lantiq/patches-3.10/0200-NET-fix-etop-registers.patch
@@ -0,0 +1,121 @@
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -47,7 +47,7 @@
+ #include <xway_dma.h>
+ #include <lantiq_platform.h>
+ 
+-#define LTQ_ETOP_MDIO         0x11804
++#define LTQ_ETOP_MDIO_ACC     0x11804
+ #define MDIO_REQUEST          0x80000000
+ #define MDIO_READ             0x40000000
+ #define MDIO_ADDR_MASK                0x1f
+@@ -56,27 +56,38 @@
+ #define MDIO_REG_OFFSET               0x10
+ #define MDIO_VAL_MASK         0xffff
+ 
+-#define PPE32_CGEN            0x800
+-#define LQ_PPE32_ENET_MAC_CFG 0x1840
++#define LTQ_ETOP_MDIO_CFG       0x11800
++#define MDIO_CFG_MASK           0x6
++
++#define LTQ_ETOP_CFG            0x11808
++#define LTQ_ETOP_IGPLEN         0x11820
++#define LTQ_ETOP_MAC_CFG      0x11840
+ 
+ #define LTQ_ETOP_ENETS0               0x11850
+ #define LTQ_ETOP_MAC_DA0      0x1186C
+ #define LTQ_ETOP_MAC_DA1      0x11870
+-#define LTQ_ETOP_CFG          0x16020
+-#define LTQ_ETOP_IGPLEN               0x16080
++
++#define MAC_CFG_MASK          0xfff
++#define MAC_CFG_CGEN          (1 << 11)
++#define MAC_CFG_DUPLEX                (1 << 2)
++#define MAC_CFG_SPEED         (1 << 1)
++#define MAC_CFG_LINK          (1 << 0)
+ 
+ #define MAX_DMA_CHAN          0x8
+ #define MAX_DMA_CRC_LEN               0x4
+ #define MAX_DMA_DATA_LEN      0x600
+ 
+ #define ETOP_FTCU             BIT(28)
+-#define ETOP_MII_MASK         0xf
+-#define ETOP_MII_NORMAL               0xd
+-#define ETOP_MII_REVERSE      0xe
+ #define ETOP_PLEN_UNDER               0x40
+-#define ETOP_CGEN             0x800
+ #define ETOP_CFG_MII0         0x01
+ 
++#define ETOP_CFG_MASK           0xfff
++#define ETOP_CFG_FEN0         (1 << 8)
++#define ETOP_CFG_SEN0         (1 << 6)
++#define ETOP_CFG_OFF1         (1 << 3)
++#define ETOP_CFG_REMII0               (1 << 1)
++#define ETOP_CFG_OFF0         (1 << 0)
++
+ #define LTQ_GBIT_MDIO_CTL     0xCC
+ #define LTQ_GBIT_MDIO_DATA    0xd0
+ #define LTQ_GBIT_GCTL0                0x68
+@@ -355,16 +366,19 @@ ltq_etop_hw_init(struct net_device *dev)
+               /* force the etops link to the gbit to MII */
+               mii_mode = PHY_INTERFACE_MODE_MII;
+       }
++      ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
++      ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
++                      MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
+ 
+       switch (mii_mode) {
+       case PHY_INTERFACE_MODE_RMII:
+-              ltq_etop_w32_mask(ETOP_MII_MASK,
+-                      ETOP_MII_REVERSE, LTQ_ETOP_CFG);
++              ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
++                      ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
+               break;
+ 
+       case PHY_INTERFACE_MODE_MII:
+-              ltq_etop_w32_mask(ETOP_MII_MASK,
+-                      ETOP_MII_NORMAL, LTQ_ETOP_CFG);
++              ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
++                      ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
+               break;
+ 
+       default:
+@@ -385,9 +399,6 @@ ltq_etop_hw_init(struct net_device *dev)
+               return -ENOTSUPP;
+       }
+ 
+-      /* enable crc generation */
+-      ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
+-
+       return 0;
+ }
+ 
+@@ -521,9 +532,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
+               ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
+               phy_data;
+ 
+-      while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++      while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+               ;
+-      ltq_etop_w32(val, LTQ_ETOP_MDIO);
++      ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
+       return 0;
+ }
+ 
+@@ -534,12 +545,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
+               ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
+               ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
+ 
+-      while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++      while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+               ;
+-      ltq_etop_w32(val, LTQ_ETOP_MDIO);
+-      while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++      ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
++      while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+               ;
+-      val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
++      val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
+       return val;
+ }
+