#define AMDGPU_VCN_FIRMWARE_OFFSET 256
#define AMDGPU_VCN_MAX_ENC_RINGS 3
+#define VCN_CMD_FENCE 0x00000000
+#define VCN_CMD_TRAP 0x00000001
+#define VCN_CMD_WRITE_REG 0x00000004
+#define VCN_CMD_REG_READ_COND_WAIT 0x00000006
+#define VCN_CMD_PACKET_START 0x0000000a
+#define VCN_CMD_PACKET_END 0x0000000b
+
struct amdgpu_vcn {
struct amdgpu_bo *vcpu_bo;
void *cpu_addr;
amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
- amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, VCN_CMD_FENCE << 1);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
- amdgpu_ring_write(ring, 2);
+ amdgpu_ring_write(ring, VCN_CMD_TRAP << 1);
}
/**
amdgpu_ring_write(ring, data1);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
- amdgpu_ring_write(ring, 8);
+ amdgpu_ring_write(ring, VCN_CMD_WRITE_REG << 1);
}
static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, mask);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
- amdgpu_ring_write(ring, 12);
+ amdgpu_ring_write(ring, VCN_CMD_REG_READ_COND_WAIT << 1);
}
static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,