drm/i915: Make IS_HASWELL only take dev_priv

Saves 2432 bytes of .rodata strings.

v2: Add parantheses around dev_priv. (Ville Syrjala)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Jani Nikula <jani.nikula@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 705b931c9249c0ddf41b3aa90fe3b964eb7546c6..6fa237739fdc7b5a01c2d248af4bfaf4f1c1d7aa 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2657,7 +2657,7 @@ struct drm_i915_cmd_table {
                                 INTEL_DEVID(dev_priv) == 0x015a)
 #define IS_VALLEYVIEW(dev)     (INTEL_INFO(dev)->is_valleyview)
 #define IS_CHERRYVIEW(dev)     (INTEL_INFO(dev)->is_cherryview)
-#define IS_HASWELL(dev)        (INTEL_INFO(dev)->is_haswell)
+#define IS_HASWELL(dev_priv)   ((dev_priv)->info.is_haswell)
 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
 #define IS_SKYLAKE(dev)        (INTEL_INFO(dev)->is_skylake)
 #define IS_BROXTON(dev)                (INTEL_INFO(dev)->is_broxton)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3ad827448b4ba681815cbdb5fcccc1b5fbffcd61..16c93cecdab527319b2164ef413923bec3848809 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4428,7 +4428,7 @@ i915_gem_init_hw(struct drm_device *dev)
        if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
                I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
-       if (IS_HASWELL(dev))
+       if (IS_HASWELL(dev_priv))
                I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
                           LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 463bf732f16f9dbb494e02ddd9c5e2830ff5024a..179f16b19515bd86c0ffb73afdc747c86767c29d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1748,7 +1748,7 @@ static void gen7_ppgtt_enable(struct drm_device *dev)
        I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 
        ecochk = I915_READ(GAM_ECOCHK);
-       if (IS_HASWELL(dev)) {
+       if (IS_HASWELL(dev_priv)) {
                ecochk |= ECOCHK_PPGTT_WB_HSW;
        } else {
                ecochk |= ECOCHK_PPGTT_LLC_IVB;
@@ -2060,7 +2060,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
        ppgtt->base.pte_encode = ggtt->base.pte_encode;
        if (intel_vgpu_active(dev_priv) || IS_GEN6(dev))
                ppgtt->switch_mm = gen6_mm_switch;
-       else if (IS_HASWELL(dev))
+       else if (IS_HASWELL(dev_priv))
                ppgtt->switch_mm = hsw_mm_switch;
        else if (IS_GEN7(dev))
                ppgtt->switch_mm = gen7_mm_switch;

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c2a960eb0290925d4ddd8ba15417bc638b653f0a..4eae1beb0d4f64c303fa8ebbfcac32d94919a9aa 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3591,8 +3591,8 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
        dev_priv->gt_irq_mask = ~0;
        if (HAS_L3_DPF(dev)) {
                /* L3 parity interrupt is always unmasked. */
-               dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
-               gt_irqs |= GT_PARITY_ERROR(dev);
+               dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
+               gt_irqs |= GT_PARITY_ERROR(dev_priv);
        }
 
        gt_irqs |= GT_RENDER_USER_INTERRUPT;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5f7aecbba5499d374cdea595c36677df769ad9d9..00efaa13974d93295275be42a06350afde86270e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2093,9 +2093,9 @@ enum skl_disp_power_wells {
 #define PM_VEBOX_CS_ERROR_INTERRUPT            (1 << 12) /* hsw+ */
 #define PM_VEBOX_USER_INTERRUPT                        (1 << 10) /* hsw+ */
 
-#define GT_PARITY_ERROR(dev) \
+#define GT_PARITY_ERROR(dev_priv) \
        (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
-        (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
+        (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
 
 /* These are all the "old" interrupts */
 #define ILK_BSD_USER_INTERRUPT                         (1<<5)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index be76ef88678c3cf65a6357fb0538984489572348..da76a799411ae6d86851ca40ab4e2ad8a23fcd37 100644 (file)
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -326,7 +326,7 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state)
         * Workaround : Do not read or write the pipe palette/gamma data while
         * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
         */
-       if (IS_HASWELL(dev) && intel_crtc_state->ips_enabled &&
+       if (IS_HASWELL(dev_priv) && intel_crtc_state->ips_enabled &&
            (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
                hsw_disable_ips(intel_crtc);
                reenable_ips = true;
@@ -537,7 +537,7 @@ void intel_color_init(struct drm_crtc *crtc)
        if (IS_CHERRYVIEW(dev)) {
                dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
                dev_priv->display.load_luts = cherryview_load_luts;
-       } else if (IS_HASWELL(dev)) {
+       } else if (IS_HASWELL(dev_priv)) {
                dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
                dev_priv->display.load_luts = haswell_load_luts;
        } else if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 35f0b7c9d0a6dc3d41a4b965957826625c9cc8da..cd7128b89b4d4de118ee34f92a0a01f1d5135a32 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1189,7 +1189,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
                         * eDP when not using the panel fitter, and when not
                         * using motion blur mitigation (which we don't
                         * support). */
-                       if (IS_HASWELL(dev) &&
+                       if (IS_HASWELL(dev_priv) &&
                            (intel_crtc->config->pch_pfit.enabled ||
                             intel_crtc->config->pch_pfit.force_thru))
                                temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6fa3a9ddd84ccce1e36567487c6d58d085c6c411..e057b5480b49bd6aa428f436fc55174776944b31 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5501,7 +5501,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
        /* If we change the relative order between pipe/planes enabling, we need
         * to change the workaround. */
        hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
-       if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
+       if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
                intel_wait_for_vblank(dev, hsw_workaround_pipe);
                intel_wait_for_vblank(dev, hsw_workaround_pipe);
        }
@@ -8299,7 +8299,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
         * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
         * documented on the DDI_FUNC_CTL register description, EDP Input Select
         * bits. */
-       if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
+       if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
            (pipe == PIPE_B || pipe == PIPE_C))
                I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
 
@@ -10026,7 +10026,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
        I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
        I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
             "CPU PWM1 enabled\n");
-       if (IS_HASWELL(dev))
+       if (IS_HASWELL(dev_priv))
                I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
                     "CPU PWM2 enabled\n");
        I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
@@ -10046,9 +10046,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
 
 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
 {
-       struct drm_device *dev = &dev_priv->drm;
-
-       if (IS_HASWELL(dev))
+       if (IS_HASWELL(dev_priv))
                return I915_READ(D_COMP_HSW);
        else
                return I915_READ(D_COMP_BDW);
@@ -10056,9 +10054,7 @@ static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
 
 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
 {
-       struct drm_device *dev = &dev_priv->drm;
-
-       if (IS_HASWELL(dev)) {
+       if (IS_HASWELL(dev_priv)) {
                mutex_lock(&dev_priv->rps.hw_lock);
                if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
                                            val))
@@ -10735,7 +10731,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
                        ironlake_get_pfit_config(crtc, pipe_config);
        }
 
-       if (IS_HASWELL(dev))
+       if (IS_HASWELL(dev_priv))
                pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
                        (I915_READ(IPS_CTL) & IPS_ENABLE);
 
@@ -13195,6 +13191,7 @@ intel_pipe_config_compare(struct drm_device *dev,
                          struct intel_crtc_state *pipe_config,
                          bool adjust)
 {
+       struct drm_i915_private *dev_priv = to_i915(dev);
        bool ret = true;
 
 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
@@ -13340,7 +13337,7 @@ intel_pipe_config_compare(struct drm_device *dev,
 
        PIPE_CONF_CHECK_I(pixel_multiplier);
        PIPE_CONF_CHECK_I(has_hdmi_sink);
-       if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
+       if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
            IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
                PIPE_CONF_CHECK_I(limited_color_range);
        PIPE_CONF_CHECK_I(has_infoframe);
@@ -13381,7 +13378,7 @@ intel_pipe_config_compare(struct drm_device *dev,
        }
 
        /* BDW+ don't expose a synchronous way to read the state */
-       if (IS_HASWELL(dev))
+       if (IS_HASWELL(dev_priv))
                PIPE_CONF_CHECK_I(ips_enabled);
 
        PIPE_CONF_CHECK_I(double_wide);
@@ -17262,7 +17259,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
                        err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
                        err_printf(m, "  POS: %08x\n", error->plane[i].pos);
                }
-               if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
+               if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
                        err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
                if (INTEL_INFO(dev)->gen >= 4) {
                        err_printf(m, "  SURF: %08x\n", error->plane[i].surface);

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index d0667f9d917884237816695e7e400569dde2e5a2..4a973b34348ac0dfa35ba3fb85db77ed70ba8cd2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -268,7 +268,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
        val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
        val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
-       if (IS_HASWELL(dev))
+       if (IS_HASWELL(dev_priv))
                val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
        if (dev_priv->psr.link_standby)
@@ -360,14 +360,14 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
                return false;
        }
 
-       if (IS_HASWELL(dev) &&
+       if (IS_HASWELL(dev_priv) &&
            I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
                      S3D_ENABLE) {
                DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
                return false;
        }
 
-       if (IS_HASWELL(dev) &&
+       if (IS_HASWELL(dev_priv) &&
            adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
                DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
                return false;