drm/meson: add RDMA register bits defines

The Amlogic VPU embeds a "Register DMA" that can write a sequence of registers
on the VPU AHB bus, either manually or triggered by an internal IRQ event like
VSYNC or a line input counter.

This adds the register defines.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-3-narmstrong@baylibre.com

diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
index 547bee04b46e7e9f6fc0a0ab8b97f77a366d3b38..8ea00546cd4e29187ee29ed9889505a258532a3e 100644 (file)
--- a/drivers/gpu/drm/meson/meson_registers.h
+++ b/drivers/gpu/drm/meson/meson_registers.h
@@ -1211,11 +1211,59 @@
 #define RDMA_AHB_START_ADDR_7 0x110e
 #define RDMA_AHB_END_ADDR_7 0x110f
 #define RDMA_ACCESS_AUTO 0x1110
+#define                RDMA_ACCESS_TRIGGER_CHAN3       GENMASK(31, 24)
+#define                RDMA_ACCESS_TRIGGER_CHAN2       GENMASK(23, 16)
+#define                RDMA_ACCESS_TRIGGER_CHAN1       GENMASK(15, 8)
+#define                RDMA_ACCESS_TRIGGER_STOP        0
+#define                RDMA_ACCESS_TRIGGER_VSYNC       1
+#define                RDMA_ACCESS_TRIGGER_LINE        32
+#define                RDMA_ACCESS_RW_FLAG_CHAN3       BIT(7)
+#define                RDMA_ACCESS_RW_FLAG_CHAN2       BIT(6)
+#define                RDMA_ACCESS_RW_FLAG_CHAN1       BIT(5)
+#define                RDMA_ACCESS_ADDR_INC_CHAN3      BIT(3)
+#define                RDMA_ACCESS_ADDR_INC_CHAN2      BIT(2)
+#define                RDMA_ACCESS_ADDR_INC_CHAN1      BIT(1)
 #define RDMA_ACCESS_AUTO2 0x1111
+#define                RDMA_ACCESS_RW_FLAG_CHAN7       BIT(7)
+#define                RDMA_ACCESS_RW_FLAG_CHAN6       BIT(6)
+#define                RDMA_ACCESS_RW_FLAG_CHAN5       BIT(5)
+#define                RDMA_ACCESS_RW_FLAG_CHAN4       BIT(4)
+#define                RDMA_ACCESS_ADDR_INC_CHAN7      BIT(3)
+#define                RDMA_ACCESS_ADDR_INC_CHAN6      BIT(2)
+#define                RDMA_ACCESS_ADDR_INC_CHAN5      BIT(1)
+#define                RDMA_ACCESS_ADDR_INC_CHAN4      BIT(0)
 #define RDMA_ACCESS_AUTO3 0x1112
+#define                RDMA_ACCESS_TRIGGER_CHAN7       GENMASK(31, 24)
+#define                RDMA_ACCESS_TRIGGER_CHAN6       GENMASK(23, 16)
+#define                RDMA_ACCESS_TRIGGER_CHAN5       GENMASK(15, 8)
+#define                RDMA_ACCESS_TRIGGER_CHAN4       GENMASK(7, 0)
 #define RDMA_ACCESS_MAN 0x1113
+#define                RDMA_ACCESS_MAN_RW_FLAG         BIT(2)
+#define                RDMA_ACCESS_MAN_ADDR_INC        BIT(1)
+#define                RDMA_ACCESS_MAN_START           BIT(0)
 #define RDMA_CTRL 0x1114
+#define                RDMA_IRQ_CLEAR_CHAN7    BIT(31)
+#define                RDMA_IRQ_CLEAR_CHAN6    BIT(30)
+#define                RDMA_IRQ_CLEAR_CHAN5    BIT(29)
+#define                RDMA_IRQ_CLEAR_CHAN4    BIT(28)
+#define                RDMA_IRQ_CLEAR_CHAN3    BIT(27)
+#define                RDMA_IRQ_CLEAR_CHAN2    BIT(26)
+#define                RDMA_IRQ_CLEAR_CHAN1    BIT(25)
+#define                RDMA_IRQ_CLEAR_CHAN_MAN BIT(24)
+#define                RDMA_DEFAULT_CONFIG     (BIT(7) | BIT(6))
+#define                RDMA_CTRL_AHB_WR_BURST  GENMASK(5, 4)
+#define                RDMA_CTRL_AHB_RD_BURST  GENMASK(3, 2)
+#define                RDMA_CTRL_SW_RESET      BIT(1)
+#define                RDMA_CTRL_FREE_CLK_EN   BIT(0)
 #define RDMA_STATUS 0x1115
+#define                RDMA_IRQ_STAT_CHAN7     BIT(31)
+#define                RDMA_IRQ_STAT_CHAN6     BIT(30)
+#define                RDMA_IRQ_STAT_CHAN5     BIT(29)
+#define                RDMA_IRQ_STAT_CHAN4     BIT(28)
+#define                RDMA_IRQ_STAT_CHAN3     BIT(27)
+#define                RDMA_IRQ_STAT_CHAN2     BIT(26)
+#define                RDMA_IRQ_STAT_CHAN1     BIT(25)
+#define                RDMA_IRQ_STAT_CHAN_MAN  BIT(24)
 #define RDMA_STATUS2 0x1116
 #define RDMA_STATUS3 0x1117
 #define L_GAMMA_CNTL_PORT 0x1400