AA: ar71xx: use the ath79_set_ar934x_eth_cfg helper in machine setup routines
authorGabor Juhos <juhosg@openwrt.org>
Thu, 18 Oct 2012 07:13:10 +0000 (07:13 +0000)
committerGabor Juhos <juhosg@openwrt.org>
Thu, 18 Oct 2012 07:13:10 +0000 (07:13 +0000)
Backport of r33818.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 33836

target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c
target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c
target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr4300.c
target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1041n-v2.c
target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c

index 1855349a392d96024c88759316603720233f5c76..f6165273d8ea5e81989e20fc6328004aaf660750 100644 (file)
@@ -175,27 +175,6 @@ static void __init om2p_lc_setup(void)
 
 MIPS_MACHINE(ATH79_MACH_OM2P_LC, "OM2P-LC", "OpenMesh OM2P LC", om2p_lc_setup);
 
-
-static void __init om2p_hs_gmac_setup(void)
-{
-       void __iomem *base;
-       u32 t;
-
-       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
-
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-
-       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
-              AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE |
-              AR934X_ETH_CFG_SW_PHY_SWAP);
-
-       t |= AR934X_ETH_CFG_SW_PHY_SWAP;
-       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-
-       iounmap(base);
-}
-
 static void __init om2p_hs_setup(void)
 {
        u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
@@ -222,7 +201,7 @@ static void __init om2p_hs_setup(void)
 
        ath79_register_wmac(art, NULL);
 
-       om2p_hs_gmac_setup();
+       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
        ath79_register_mdio(1, 0x0);
 
        ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
index ecdd7ea2e89f00a2968ffaf3b8a374b41e6dfe9d..933a45130954d3ce85c0f3f01070b7246460500b 100644 (file)
@@ -123,23 +123,6 @@ static struct mdio_board_info rb2011_mdio0_info[] = {
        },
 };
 
-static void __init rb2011_gmac_setup(void)
-{
-       void __iomem *base;
-       u32 t;
-
-       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
-
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
-               AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
-       t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
-
-       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
-
-       iounmap(base);
-}
-
 static void __init rb2011_wlan_init(void)
 {
        u8 *hard_cfg = (u8 *) KSEG1ADDR(0x1f000000 + RB_HARD_CFG_OFFSET);
@@ -232,7 +215,8 @@ static void __init rb2011_setup(void)
        ath79_register_m25p80(&rb2011_spi_flash_data);
        rb2011_nand_init();
 
-       rb2011_gmac_setup();
+       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
+                                  AR934X_ETH_CFG_SW_ONLY_MODE);
 
        ath79_register_mdio(1, 0x0);
        ath79_register_mdio(0, 0x0);
index 331de5680bc8ae31129601efca0159033dfde339..483aa6e935f533ec732897e39f1c7af437bdd20c 100644 (file)
@@ -139,23 +139,6 @@ static struct mdio_board_info wdr4300_mdio0_info[] = {
        },
 };
 
-static void __init wdr4300_gmac_setup(void)
-{
-       void __iomem *base;
-       u32 t;
-
-       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
-
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
-              AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
-       t |= AR934X_ETH_CFG_RGMII_GMAC0;
-
-       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
-
-       iounmap(base);
-}
-
 static void __init wdr4300_setup(void)
 {
        u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
@@ -176,7 +159,7 @@ static void __init wdr4300_setup(void)
        ap9x_pci_setup_wmac_led_pin(0, 0);
        ap91_pci_init(art + WDR4300_PCIE_CALDATA_OFFSET, tmpmac);
 
-       wdr4300_gmac_setup();
+       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
 
        mdiobus_register_board_info(wdr4300_mdio0_info,
                                    ARRAY_SIZE(wdr4300_mdio0_info));
index ed5b2b0e6393929b8b9c9232e6289d949baba1ff..163dc6fa631a1dd4eca202f4094ca90c368a1a60 100644 (file)
@@ -101,23 +101,6 @@ static struct mdio_board_info db120_mdio0_info[] = {
        },
 };
 
-static void __init db120_gmac_setup(void)
-{
-       void __iomem *base;
-       u32 t;
-
-       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
-
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
-              AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
-       t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
-
-       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
-
-       iounmap(base);
-}
-
 static void __init tl_wr1041nv2_setup(void)
 {
        u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
@@ -132,7 +115,8 @@ static void __init tl_wr1041nv2_setup(void)
                                         tl_wr1041nv2_gpio_keys);
        ath79_register_wmac(ee, mac);
 
-       db120_gmac_setup();
+       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
+                                  AR934X_ETH_CFG_SW_ONLY_MODE);
 
        ath79_register_mdio(1, 0x0);
        ath79_register_mdio(0, 0x0);
index db4d1052ab008f8d8550596d65d2423076494701..ffaf8d1552634b8e3e4cb41e539a7709c5872163 100644 (file)
@@ -99,26 +99,6 @@ static struct gpio_keys_button tl_wr841n_v8_gpio_keys[] __initdata = {
        }
 };
 
-static void __init tl_wr841n_v8_gmac_setup(void)
-{
-       void __iomem *base;
-       u32 t;
-
-       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
-
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-
-       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
-              AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE |
-              AR934X_ETH_CFG_SW_PHY_SWAP);
-
-       t |= AR934X_ETH_CFG_SW_PHY_SWAP;
-       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-
-       iounmap(base);
-}
-
 static void __init tl_wr841n_v8_setup(void)
 {
        u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
@@ -133,7 +113,7 @@ static void __init tl_wr841n_v8_setup(void)
 
        ath79_register_m25p80(&tl_wr841n_v8_flash_data);
 
-       tl_wr841n_v8_gmac_setup();
+       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
 
        ath79_register_mdio(1, 0x0);