sh: Add support ESPT-GIGA borad

ESPT-Giga is SH7763-based reference board.
Board support is relatively sparse, presently supporting serial,
gigabit ethernet, USB host, and MTD.

More information (in Japanese) available at:
http://www.cente.jp/product/cente_hard/ESPT-Giga.html

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/MAKEALL b/MAKEALL
index 41f144553e0e579e9467b65557e1fcd3629b1c97..2b42352b5de1b8982ed2e82f03fadefa5217cc17 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -848,6 +848,7 @@ LIST_sh4="          \
        sh7763rdp       \
        sh7785lcr       \
        ap325rxa        \
+       espt            \
 "
 
 LIST_sh="              \

diff --git a/Makefile b/Makefile
index 8d0510366be5ccde965d16b3a8756c48510d52ec..0d607cad54986377426a5e529045c818bf740e67 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -3545,6 +3545,11 @@ ap325rxa_config  :   unconfig
        @echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h
        @$(MKCONFIG) -a $(@:_config=) sh sh4 ap325rxa renesas
 
+espt_config  :   unconfig
+       @mkdir -p $(obj)include
+       @echo "#define CONFIG_ESPT 1" > $(obj)include/config.h
+       @$(MKCONFIG) -a $(@:_config=) sh sh4 espt
+
 #========================================================================
 # SPARC
 #========================================================================

diff --git a/board/espt/Makefile b/board/espt/Makefile
new file mode 100644 (file)
index 0000000..c79cba8
--- /dev/null
+++ b/board/espt/Makefile
@@ -0,0 +1,50 @@
+#
+# Copyright (C) 2009 Renesas Solutions Corp.
+# Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+#
+# board/espt/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS  := espt.o
+SOBJS  := lowlevel_init.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

diff --git a/board/espt/config.mk b/board/espt/config.mk
new file mode 100644 (file)
index 0000000..006b432
--- /dev/null
+++ b/board/espt/config.mk
@@ -0,0 +1,9 @@
+#
+# board/espt/config.mk
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000

diff --git a/board/espt/espt.c b/board/espt/espt.c
new file mode 100644 (file)
index 0000000..2930858
--- /dev/null
+++ b/board/espt/espt.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * board/espt/espt.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+       puts("BOARD: ESPT-GIGA\n");
+       return 0;
+}
+
+int board_init(void)
+{
+       return 0;
+}
+
+int dram_init(void)
+{
+       DECLARE_GLOBAL_DATA_PTR;
+
+       gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+       gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+       printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+       return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}

diff --git a/board/espt/lowlevel_init.S b/board/espt/lowlevel_init.S
new file mode 100644 (file)
index 0000000..7d5d72e
--- /dev/null
+++ b/board/espt/lowlevel_init.S
@@ -0,0 +1,334 @@
+/*
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * board/espt/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+       .global lowlevel_init
+
+       .text
+       .align  2
+
+lowlevel_init:
+
+       write32 WDTCSR_A, WDTCSR_D
+
+       write32 WDTST_A, WDTST_D
+
+       write32 WDTBST_A, WDTBST_D
+
+       write32 CCR_A, CCR_CACHE_ICI_D
+
+       write32 MMUCR_A, MMU_CONTROL_TI_D
+
+       write32 MSTPCR0_A, MSTPCR0_D
+
+       write32 MSTPCR1_A, MSTPCR1_D
+
+       write32 RAMCR_A, RAMCR_D
+
+       /*
+        * Setting infomation from
+        * original ESPT-GIGA bootloader register
+        */
+       write32 MMSEL_A, MMSEL_D
+
+       /* dummy */
+       mov.l   @r1, r2
+       mov.l   @r1, r2
+       synco
+
+    write32 BCR_A, BCR_D
+
+    write32 CS0BCR_A, CS0BCR_D
+
+    write32 CS0WCR_A, CS0WCR_D
+
+       /*
+        * DDR-SDRAM setting
+        */
+
+       /* set DDR-SDRAM dummy read */
+       write32 MMSEL_A, MMSEL_D
+
+       mov.l   MMSEL_A, r0
+       synco
+       mov.l   @r0, r1
+       synco
+
+       mov.l   CS0_A, r0
+       synco
+       mov.l   @r0, r1
+       synco
+
+       /* set DDR-SDRAM bus/endian etc */
+       write32 MIM_U_A, MIM_U_D
+
+       write32 MIM_L_A, MIM_L_D0
+
+       write32 SDR_L_A, SDR_L_A_D0
+
+       write32 STR_L_A, STR_L_A_D0
+
+       /* DDR-SDRAM access control */
+       write32 MIM_L_A, MIM_L_D1
+
+       write32 SCR_L_A, SCR_L_A_D0
+
+       write32 SCR_L_A, SCR_L_A_D1
+
+       write32 EMRS_A, EMRS_D
+
+       write32 MRS1_A, MRS1_D
+
+       write32 MIM_U_A, MIM_U_D
+
+       write32 MIM_L_A, MIM_L_A_D2
+
+       write32 SCR_L_A, SCR_L_A_D2
+
+       write32 SCR_L_A, SCR_L_A_D2
+
+       write32 MRS2_A, MRS2_D
+
+       /* wait 200us */
+       wait_timer REPEAT_R3
+
+       /* GPIO setting */
+       write16 PSEL0_A, PSEL0_D
+
+       write16 PSEL1_A, PSEL1_D
+
+       write16 PSEL2_A, PSEL2_D
+
+       write16 PSEL3_A, PSEL3_D
+
+       write16 PSEL4_A, PSEL4_D
+
+       write8 PADR_A, PADR_D
+
+       write16 PACR_A, PACR_D
+
+       write8 PBDR_A, PBDR_D
+
+       write16 PBCR_A, PBCR_D
+
+       write8 PCDR_A, PCDR_D
+
+       write16 PCCR_A, PCCR_D
+
+       write8  PDDR_A, PDDR_D
+
+       write16 PDCR_A, PDCR_D
+
+       write16 PECR_A, PECR_D
+
+       write16 PFCR_A, PFCR_D
+
+       write16 PGCR_A, PGCR_D
+
+       write16 PHCR_A, PHCR_D
+
+       write16 PICR_A, PICR_D
+
+       write8 PJDR_A, PJDR_D
+
+       write16 PJCR_A, PJCR_D
+
+       /* wait 50us */
+       wait_timer REPEAT_R3
+
+       write8 PKDR_A, PKDR_D
+
+       write16 PKCR_A, PKCR_D
+
+       write16 PLCR_A, PLCR_D
+
+       write16 PMCR_A, PMCR_D
+
+       write16 PNCR_A, PNCR_D
+
+       write16 POCR_A, POCR_D
+
+
+       /* ICR0 ,ICR1 */
+       write32 ICR0_A, ICR0_D
+
+       write32 ICR1_A, ICR1_D
+
+       /* USB Host */
+       write32 USB_USBHSC_A, USB_USBHSC_D
+
+       write32 CCR_A, CCR_CACHE_D_2
+
+       rts
+       nop
+
+       .align  2
+
+/* GPIO Crontrol Register */
+PACR_A:        .long   0xFFEF0000
+PBCR_A:        .long   0xFFEF0002
+PCCR_A:        .long   0xFFEF0004
+PDCR_A:        .long   0xFFEF0006
+PECR_A:        .long   0xFFEF0008
+PFCR_A:        .long   0xFFEF000A
+PGCR_A:        .long   0xFFEF000C
+PHCR_A:        .long   0xFFEF000E
+PICR_A:        .long   0xFFEF0010
+PJCR_A:        .long   0xFFEF0012
+PKCR_A:        .long   0xFFEF0014
+PLCR_A:        .long   0xFFEF0016
+PMCR_A:        .long   0xFFEF0018
+PNCR_A:        .long   0xFFEF001A
+POCR_A:        .long   0xFFEF001C
+
+/* GPIO Data Register */
+PADR_A:        .long   0xFFEF0020
+PBDR_A:        .long   0xFFEF0022
+PCDR_A:        .long   0xFFEF0024
+PDDR_A:        .long   0xFFEF0026
+PJDR_A:        .long   0xFFEF0032
+PKDR_A:        .long   0xFFEF0034
+
+/* GPIO Set data */
+PADR_D:        .long   0x00000000
+PACR_D:        .long   0x00001400
+PBDR_D:        .long   0x00000000
+PBCR_D:        .long   0x0000555A
+PCDR_D:        .long   0x00000000
+PCCR_D:        .long   0x00005555
+PDDR_D:        .long   0x00000000
+PDCR_D:        .long   0x00000155
+PECR_D:        .long   0x00000000
+PFCR_D:        .long   0x00000000
+PGCR_D:        .long   0x00000000
+PHCR_D:        .long   0x00000000
+PICR_D:        .long   0x00000800
+PJDR_D:        .long   0x00000006
+PJCR_D:        .long   0x00005A57
+PKDR_D:        .long   0x00000000
+PKCR_D:        .long   0x0000FFF9
+PLCR_D:        .long   0x0000C330
+PMCR_D:        .long   0x0000FFFF
+PNCR_D:        .long   0x00000242
+POCR_D:        .long   0x00000000
+
+/* Pin Select */
+PSEL0_A:       .long   0xFFEF0070
+PSEL1_A:       .long   0xFFEF0072
+PSEL2_A:       .long   0xFFEF0074
+PSEL3_A:       .long   0xFFEF0076
+PSEL4_A:       .long   0xFFEF0078
+PSEL0_D:       .long   0x0001
+PSEL1_D:       .long   0x2400
+PSEL2_D:       .long   0x0000
+PSEL3_D:       .long   0x2421
+PSEL4_D:       .long   0x0000
+
+MMSEL_A:       .long   0xFE600020
+BCR_A:         .long   0xFF801000
+CS0BCR_A:      .long   0xFF802000
+CS0WCR_A:      .long   0xFF802008
+ICR0_A:                .long   0xFFD00000
+ICR1_A:                .long   0xFFD0001C
+
+MMSEL_D:       .long   0xA5A50000
+BCR_D:         .long   0x05000000
+CS0BCR_D:      .long   0x232306F0
+CS0WCR_D:      .long   0x00011104
+ICR0_D:                .long   0x80C00000
+ICR1_D:                .long   0x00020000
+
+/* RWBT Address */
+WDTST_A:       .long   0xFFCC0000
+WDTCSR_A:      .long   0xFFCC0004
+WDTBST_A:      .long   0xFFCC0008
+/* RWBT Data */
+WDTST_D:       .long   0x5A000FFF
+WDTCSR_D:      .long   0xA5000000
+WDTBST_D:      .long   0x55000000
+
+/* Cache Address */
+CCR_A:         .long   0xFF00001C
+MMUCR_A:       .long   0xFF000010
+RAMCR_A:       .long   0xFF000074
+
+/* Cache Data */
+CCR_CACHE_ICI_D:.long  0x00000800
+CCR_CACHE_D_2: .long   0x00000103
+MMU_CONTROL_TI_D:.long 0x00000004
+RAMCR_D:       .long   0x00000200
+
+/* Low power mode control Address */
+MSTPCR0_A:     .long   0xFFC80030
+MSTPCR1_A:     .long   0xFFC80038
+/* Low power mode control Data */
+MSTPCR0_D:     .long   0x00000000
+MSTPCR1_D:     .long   0x00000000
+
+REPEAT0_R3:    .long   0x00002000
+REPEAT_R3:     .long   0x00000200
+CS0_A:         .long   0xA8000000
+
+MIM_U_A:       .long   0xFE800008
+MIM_L_A:       .long   0xFE80000C
+SCR_U_A:       .long   0xFE800010
+SCR_L_A:       .long   0xFE800014
+STR_U_A:       .long   0xFE800018
+STR_L_A:       .long   0xFE80001C
+SDR_U_A:       .long   0xFE800030
+SDR_L_A:       .long   0xFE800034
+EMRS_A:                .long   0xFE902000
+MRS1_A:                .long   0xFE900B08
+MRS2_A:                .long   0xFE900308
+
+MIM_U_D:       .long   0x00000000
+MIM_L_D0:      .long   0x04100008
+MIM_L_D1:      .long   0x02EE0009
+MIM_L_D2:      .long   0x02EE0209
+
+SDR_L_A_D0:    .long   0x00000300
+STR_L_A_D0:    .long   0x00010040
+MIM_L_A_D1:    .long   0x04100009
+SCR_L_A_D0:    .long   0x00000003
+SCR_L_A_D1:    .long   0x00000002
+MIM_L_A_D2:    .long   0x04100209
+SCR_L_A_D2:    .long   0x00000004
+
+SCR_L_NORMAL:  .long   0x00000000
+SCR_L_NOP:             .long   0x00000001
+SCR_L_PALL:            .long   0x00000002
+SCR_L_CKE_EN:  .long   0x00000003
+SCR_L_CBR:             .long   0x00000004
+
+STR_L_D:       .long   0x000F3980
+SDR_L_D:       .long   0x00000400
+EMRS_D:                .long   0x00000000
+MRS1_D:                .long   0x00000000
+MRS2_D:                .long   0x00000000
+
+/* USB */
+USB_USBHSC_A:  .long   0xFFEC80F0
+USB_USBHSC_D:  .long   0x00000000

diff --git a/include/configs/espt.h b/include/configs/espt.h
new file mode 100644 (file)
index 0000000..2ec907c
--- /dev/null
+++ b/include/configs/espt.h
@@ -0,0 +1,126 @@
+/*
+ * Configuation settings for the ESPT-GIGA board
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ESPT_H
+#define __ESPT_H
+
+#define CONFIG_SH              1
+#define CONFIG_SH4             1
+#define CONFIG_CPU_SH7763      1
+#define CONFIG_ESPT    1
+#define __LITTLE_ENDIAN                1
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_BOOTDELAY        -1
+#define CONFIG_BOOTARGS         "console=ttySC0,115200 root=1f01"
+#define CONFIG_ENV_OVERWRITE    1
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE            1
+#define CONFIG_BAUDRATE         115200
+#define CONFIG_CONS_SCIF0              1
+
+#define CONFIG_SYS_LONGHELP            /* undef to save memory */
+#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE              256     /* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE              256     /* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS             16      /* max args accepted for monitor commands */
+#define CONFIG_SYS_BARGSIZE    512     /* Buffer size for Boot Arguments
+                                                               passed to kernel */
+#define CONFIG_SYS_BAUDRATE_TABLE      { 115200 }      /* List of legal baudrate
+                                                                                               settings for this board */
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE          (0x8C000000)
+#define CONFIG_SYS_SDRAM_SIZE          (64 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START       (CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Flash(NOR) S29JL064H */
+#define CONFIG_SYS_FLASH_BASE          (0xA0000000)
+#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
+#define CONFIG_SYS_MAX_FLASH_BANKS (1)
+#define CONFIG_SYS_MAX_FLASH_SECT  (150)
+
+/* U-boot setting */
+#define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE        (CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_LEN         (128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN          (1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE       (256)
+#define CONFIG_SYS_BOOTMAPSZ           (8 * 1024 * 1024)
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO    /* print 'E' for empty sector on flinfo */
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    (3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    (3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT             (3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT   (3 * 1000)
+/* Use hardware flash sectors protection instead of U-Boot software protection */
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE   (128 * 1024)
+#define CONFIG_ENV_SIZE                (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET              (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
+
+/* Clock */
+#define CONFIG_SYS_CLK_FREQ    66666666
+#define CONFIG_SYS_TMU_CLK_DIV      4
+#define CONFIG_SYS_HZ       1000
+
+/* Ether */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_SH_ETHER 1
+#define CONFIG_SH_ETHER_USE_PORT (1)
+#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
+
+#endif /* __SH7763RDP_H */