Move translation tables into separate section

This patch moves the translation tables into their own section. This
saves space that would otherwise have been lost in padding due to page
table alignment constraints. The BL31 and BL32 bases have been
consequently adjusted.

Change-Id: Ibd65ae8a5ce4c4ea9a71a794c95bbff40dc63e65

diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S
index 48828e8f7bdbe2a120604b83a4bd56856c281b2e..969b8c275490e40bcb736e20d5294edd24ef1b57 100644 (file)
--- a/bl1/bl1.ld.S
+++ b/bl1/bl1.ld.S
@@ -76,6 +76,15 @@ SECTIONS
         __BSS_END__ = .;
     } >RAM
 
+    /*
+     * The .xlat_table section is for full, aligned page tables (4K).
+     * Removing them from .bss avoids forcing 4K alignment on
+     * the .bss section and eliminates the unecessary zero init
+     */
+    xlat_table (NOLOAD) : {
+        *(xlat_table)
+    } >RAM
+
     /*
      * The base address of the coherent memory section must be page-aligned (4K)
      * to guarantee that the coherent data are stored on their own pages and

diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S
index c1d5d5c2fd89bafeacf40dff8938b458343ea758..849297a74db2530c5de27402b6ec9b52de196027 100644 (file)
--- a/bl2/bl2.ld.S
+++ b/bl2/bl2.ld.S
@@ -59,6 +59,15 @@ SECTIONS
         __RO_END__ = .;
     } >RAM
 
+    /*
+     * The .xlat_table section is for full, aligned page tables (4K).
+     * Removing them from .bss avoids forcing 4K alignment on
+     * the .bss section and eliminates the unecessary zero init
+     */
+    xlat_table (NOLOAD) : {
+        *(xlat_table)
+    } >RAM
+
     .data . : {
         __DATA_START__ = .;
         *(.data)

diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 423256095bd9fed6543533386d0c3cb074ea1ff5..7cc85273fc377a65580b168c6da825bf0740e44a 100644 (file)
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -60,6 +60,15 @@ SECTIONS
         __RO_END__ = .;
     } >RAM
 
+    /*
+     * The .xlat_table section is for full, aligned page tables (4K).
+     * Removing them from .bss avoids forcing 4K alignment on
+     * the .bss section and eliminates the unecessary zero init
+     */
+    xlat_table (NOLOAD) : {
+        *(xlat_table)
+    } >RAM
+
     .data . : {
         __DATA_START__ = .;
         *(.data)

diff --git a/plat/fvp/aarch64/plat_common.c b/plat/fvp/aarch64/plat_common.c
index 5b53aafb8b99d98925954e88853affbd3a54912b..c8c36d7900d64f836e62fcce0cff3fae97e5098a 100644 (file)
--- a/plat/fvp/aarch64/plat_common.c
+++ b/plat/fvp/aarch64/plat_common.c
@@ -67,14 +67,14 @@ __attribute__ ((aligned((ADDR_SPACE_SIZE >> 30) << 3)));
  * space needed to address secure peripherals e.g. trusted ROM and RAM.
  ******************************************************************************/
 static unsigned long l2_xlation_table[NUM_L2_PAGETABLES][NUM_2MB_IN_GB]
-__attribute__ ((aligned(NUM_2MB_IN_GB << 3)));
+__attribute__ ((aligned(NUM_2MB_IN_GB << 3), section("xlat_table")));
 
 /*******************************************************************************
  * Level 3 translation tables (2 sets) describe the trusted & non-trusted RAM
  * regions at a granularity of 4K.
  ******************************************************************************/
 static unsigned long l3_xlation_table[NUM_L3_PAGETABLES][NUM_4K_IN_2MB]
-__attribute__ ((aligned(NUM_4K_IN_2MB << 3)));
+__attribute__ ((aligned(NUM_4K_IN_2MB << 3), section("xlat_table")));
 
 /*******************************************************************************
  * Helper to create a level 1/2 table descriptor which points to a level 2/3

diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h
index a12a0948dc0f335838a7090a34b3e5526d332d3d..5826d35736d14d34fffde1540f3f216ef984833c 100644 (file)
--- a/plat/fvp/platform.h
+++ b/plat/fvp/platform.h
@@ -225,12 +225,12 @@
 /*******************************************************************************
  * BL2 specific defines.
  ******************************************************************************/
-#define BL2_BASE                       0x0402B000
+#define BL2_BASE                       0x0402D000
 
 /*******************************************************************************
  * BL31 specific defines.
  ******************************************************************************/
-#define BL31_BASE                      0x0400E000
+#define BL31_BASE                      0x0400C000
 
 /*******************************************************************************
  * Platform specific page table and MMU setup constants