n1sdp: fix DMC ECC enablement sequence in N1SDP platform

The DMC-620 memory controllers in N1SDP platform has to be put
into CONFIG state before writing to ERR0CTLR0 register to enable
ECC.

This patch fixes the sequence so that DMCs are set to CONFIG
state before writing to ERR0CTLR0 register and moved back to
READY state after writing.

Change-Id: I1252f3ae0991603bb29234029cddb5fbf869c1b2
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
index a831b89f2ca91af1f2fc7d5f77204ae3c3b6378e..632af7b409f223d529d7094af89b41adbb9e8d78 100644 (file)
--- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
+++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
@@ -80,8 +80,17 @@ void dmc_ecc_setup(uint32_t ddr_size_gb)
        flush_dcache_range(ARM_DRAM2_BASE, dram2_size);
 
        INFO("Enabling ECC on DMCs\n");
+       /* Set DMCs to CONFIG state before writing ERR0CTLR0 register */
+       mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
+       mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
+
+       /* Enable ECC in DMCs */
        mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
        mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
+
+       /* Set DMCs to READY state */
+       mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
+       mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
 }
 
 void copy_bl33(uint32_t src, uint32_t dst, uint32_t size)

diff --git a/plat/arm/board/n1sdp/n1sdp_def.h b/plat/arm/board/n1sdp/n1sdp_def.h
index b7f7213d626d0b5a8e2ac2bc1bb8d797ff4eb84b..d43c5a47b96d887bda2a1f10530405672b1af3b2 100644 (file)
--- a/plat/arm/board/n1sdp/n1sdp_def.h
+++ b/plat/arm/board/n1sdp/n1sdp_def.h
@@ -25,10 +25,18 @@
 #define N1SDP_SDS_BL33_INFO_OFFSET             0
 #define N1SDP_SDS_BL33_INFO_SIZE               12
 
+/* DMC memory command registers */
+#define N1SDP_DMC0_MEMC_CMD_REG                        0x4E000008
+#define N1SDP_DMC1_MEMC_CMD_REG                        0x4E100008
+
 /* DMC ERR0CTLR0 registers */
 #define N1SDP_DMC0_ERR0CTLR0_REG               0x4E000708
 #define N1SDP_DMC1_ERR0CTLR0_REG               0x4E100708
 
+/* DMC memory commands */
+#define N1SDP_DMC_MEMC_CMD_CONFIG              0
+#define N1SDP_DMC_MEMC_CMD_READY               3
+
 /* DMC ECC enable bit in ERR0CTLR0 register */
 #define N1SDP_DMC_ERR0CTLR0_ECC_EN             0x1