In
48ec5291, only TX path was optimized; this does the same also for RX
path. This results in huge increase of TFTP throughput on custom am3352
board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer
timeouts.
Signed-off-by: Vladimir Koutny <vladimir.koutny@streamunlimited.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Tom Rini <trini@ti.com>
void *buffer;
int len;
- cpsw_update_link(priv);
+ cpsw_check_link(priv);
while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) {
invalidate_dcache_range((unsigned long)buffer,