PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
+ PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
PDC_FLASH_CTL = 0x44, /* Flash control register */
* know when to time out the outer loop.
*/
for(i = 0; i < 1000; ++i) {
- status = readb(port_mmio + 0x38); /* altstatus */
+ status = readb(port_mmio + PDC_ALTSTATUS);
if (status == 0xFF)
break;
if (status & ATA_BUSY)
mdelay(1);
}
if (i >= 1000)
- ata_port_printk(ap, KERN_WARNING, "%s timed out", __FUNCTION__);
+ ata_port_printk(ap, KERN_WARNING, "%s timed out\n", __FUNCTION__);
+ return status;
+}
+
+static unsigned int pdc_wait_on_busy(struct ata_port *ap)
+{
+ unsigned int status = ata_busy_wait(ap, ATA_BUSY, 1000);
+ if (status != 0xff && (status & ATA_BUSY))
+ ata_port_printk(ap, KERN_WARNING, "%s timed out\n", __FUNCTION__);
return status;
}
tmp |= ATA_DEV1;
}
writeb(tmp, port_mmio + PDC_DEVICE);
- ata_busy_wait(ap, ATA_BUSY, 1000);
+ pdc_wait_on_busy(ap);
writeb(0x00, port_mmio + PDC_SECTOR_COUNT);
writeb(0x00, port_mmio + PDC_SECTOR_NUMBER);
/* send ATAPI packet command 0xA0 */
writeb(ATA_CMD_PACKET, port_mmio + PDC_COMMAND);
- /*
- * At this point in the issuing of a packet command, the Promise
- * driver busy-waits for INT (CTLSTAT bit 27) if it detected
- * (at port init time) that the device interrupts with assertion
- * of DRQ after receiving a packet command.
- *
- * XXX: Do we need to handle this case as well? Does libata detect
- * this case for us, or do we have to do our own per-port init?
+ /* pdc_qc_issue_prot() currently sends ATAPI PIO packets back
+ * to libata. If we start handling those packets ourselves,
+ * then we must busy-wait for INT (CTLSTAT bit 27) at this point
+ * if the device has ATA_DFLAG_CDB_INTR set.
*/
pdc_wait_for_drq(ap);