};
DRXJData_t DRXJData_g = {
- FALSE, /* hasLNA : TRUE if LNA (aka PGA) present */
- FALSE, /* hasOOB : TRUE if OOB supported */
- FALSE, /* hasNTSC: TRUE if NTSC supported */
- FALSE, /* hasBTSC: TRUE if BTSC supported */
- FALSE, /* hasSMATX: TRUE if SMA_TX pin is available */
- FALSE, /* hasSMARX: TRUE if SMA_RX pin is available */
- FALSE, /* hasGPIO : TRUE if GPIO pin is available */
- FALSE, /* hasIRQN : TRUE if IRQN pin is available */
+ false, /* hasLNA : true if LNA (aka PGA) present */
+ false, /* hasOOB : true if OOB supported */
+ false, /* hasNTSC: true if NTSC supported */
+ false, /* hasBTSC: true if BTSC supported */
+ false, /* hasSMATX: true if SMA_TX pin is available */
+ false, /* hasSMARX: true if SMA_RX pin is available */
+ false, /* hasGPIO : true if GPIO pin is available */
+ false, /* hasIRQN : true if IRQN pin is available */
0, /* mfx A1/A2/A... */
/* tuner settings */
- FALSE, /* tuner mirrors RF signal */
+ false, /* tuner mirrors RF signal */
/* standard/channel settings */
DRX_STANDARD_UNKNOWN, /* current standard */
DRX_CONSTELLATION_AUTO, /* constellation */
204 * 8, /* fecRsPlen annex A */
1, /* fecRsPrescale */
FEC_RS_MEASUREMENT_PERIOD, /* fecRsPeriod */
- TRUE, /* resetPktErrAcc */
+ true, /* resetPktErrAcc */
0, /* pktErrAccStart */
/* HI configuration */
DRX_UIO_MODE_DISABLE, /* uioIRQNMode */
/* FS setting */
0UL, /* iqmFsRateOfs */
- FALSE, /* posImage */
+ false, /* posImage */
/* RC setting */
0UL, /* iqmRcRateOfs */
/* AUD information */
-/* FALSE, * flagSetAUDdone */
-/* FALSE, * detectedRDS */
-/* TRUE, * flagASDRequest */
-/* FALSE, * flagHDevClear */
-/* FALSE, * flagHDevSet */
+/* false, * flagSetAUDdone */
+/* false, * detectedRDS */
+/* true, * flagASDRequest */
+/* false, * flagHDevClear */
+/* false, * flagHDevSet */
/* (u16) 0xFFF, * rdsLastCount */
/*#ifdef DRXJ_SPLIT_UCODE_UPLOAD
- FALSE, * flagAudMcUploaded */
+ false, * flagAudMcUploaded */
/*#endif * DRXJ_SPLIT_UCODE_UPLOAD */
/* ATV configuartion */
0UL, /* flags cfg changes */
ATV_TOP_EQU3_EQU_C3_BG,
ATV_TOP_EQU3_EQU_C3_DK,
ATV_TOP_EQU3_EQU_C3_I},
- FALSE, /* flag: TRUE=bypass */
+ false, /* flag: true=bypass */
ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */
ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */
- TRUE, /* flag CVBS ouput enable */
- FALSE, /* flag SIF ouput enable */
+ true, /* flag CVBS ouput enable */
+ false, /* flag SIF ouput enable */
DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */
{ /* qamRfAgcCfg */
DRX_STANDARD_ITU_B, /* standard */
{ /* qamPreSawCfg */
DRX_STANDARD_ITU_B, /* standard */
0, /* reference */
- FALSE /* usePreSaw */
+ false /* usePreSaw */
},
{ /* vsbPreSawCfg */
DRX_STANDARD_8VSB, /* standard */
0, /* reference */
- FALSE /* usePreSaw */
+ false /* usePreSaw */
},
/* Version information */
}
},
#endif
- FALSE, /* smartAntInverted */
+ false, /* smartAntInverted */
/* Tracking filter setting for OOB */
{
12000,
3000,
2000,
0},
- FALSE, /* oobPowerOn */
+ false, /* oobPowerOn */
0, /* mpegTsStaticBitrate */
- FALSE, /* disableTEIhandling */
- FALSE, /* bitReverseMpegOutout */
+ false, /* disableTEIhandling */
+ false, /* bitReverseMpegOutout */
DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpegOutputClockRate */
DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpegStartWidth */
{
DRX_STANDARD_NTSC, /* standard */
7, /* reference */
- TRUE /* usePreSaw */
+ true /* usePreSaw */
},
{ /* ATV RF-AGC */
DRX_STANDARD_NTSC, /* standard */
140, /* ATV PGA config */
0, /* currSymbolRate */
- FALSE, /* pdrSafeMode */
+ false, /* pdrSafeMode */
SIO_PDR_GPIO_CFG__PRE, /* pdrSafeRestoreValGpio */
SIO_PDR_VSYNC_CFG__PRE, /* pdrSafeRestoreValVSync */
SIO_PDR_SMA_RX_CFG__PRE, /* pdrSafeRestoreValSmaRx */
4, /* oobPreSaw */
DRXJ_OOB_LO_POW_MINUS10DB, /* oobLoPow */
{
- FALSE /* audData, only first member */
+ false /* audData, only first member */
},
};
DRXCommonAttr_t DRXJDefaultCommAttr_g = {
(u8 *) NULL, /* ucode ptr */
0, /* ucode size */
- TRUE, /* ucode verify switch */
+ true, /* ucode verify switch */
{0}, /* version record */
44000, /* IF in kHz in case no tuner instance is used */
(151875 - 0), /* system clock frequency in kHz */
0, /* oscillator frequency kHz */
0, /* oscillator deviation in ppm, signed */
- FALSE, /* If TRUE mirror frequency spectrum */
+ false, /* If true mirror frequency spectrum */
{
/* MPEG output configuration */
- TRUE, /* If TRUE, enable MPEG ouput */
- FALSE, /* If TRUE, insert RS byte */
- TRUE, /* If TRUE, parallel out otherwise serial */
- FALSE, /* If TRUE, invert DATA signals */
- FALSE, /* If TRUE, invert ERR signal */
- FALSE, /* If TRUE, invert STR signals */
- FALSE, /* If TRUE, invert VAL signals */
- FALSE, /* If TRUE, invert CLK signals */
- TRUE, /* If TRUE, static MPEG clockrate will
+ true, /* If true, enable MPEG ouput */
+ false, /* If true, insert RS byte */
+ true, /* If true, parallel out otherwise serial */
+ false, /* If true, invert DATA signals */
+ false, /* If true, invert ERR signal */
+ false, /* If true, invert STR signals */
+ false, /* If true, invert VAL signals */
+ false, /* If true, invert CLK signals */
+ true, /* If true, static MPEG clockrate will
be used, otherwise clockrate will
adapt to the bitrate of the TS */
19392658UL, /* Maximum bitrate in b/s in case
DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */
},
/* Initilisations below can be ommited, they require no user input and
- are initialy 0, NULL or FALSE. The compiler will initialize them to these
+ are initialy 0, NULL or false. The compiler will initialize them to these
values when ommited. */
- FALSE, /* isOpened */
+ false, /* isOpened */
/* SCAN */
NULL, /* no scan params yet */
0, /* current scan index */
0, /* next scan frequency */
- FALSE, /* scan ready flag */
+ false, /* scan ready flag */
0, /* max channels to scan */
0, /* nr of channels scanned */
NULL, /* default scan function */
NULL, /* default context pointer */
0, /* millisec to wait for demod lock */
DRXJ_DEMOD_LOCK, /* desired lock */
- FALSE,
+ false,
/* Power management */
DRX_POWER_UP,
1, /* nr of I2C port to wich tuner is */
0L, /* minimum RF input frequency, in kHz */
0L, /* maximum RF input frequency, in kHz */
- FALSE, /* Rf Agc Polarity */
- FALSE, /* If Agc Polarity */
- FALSE, /* tuner slow mode */
+ false, /* Rf Agc Polarity */
+ false, /* If Agc Polarity */
+ false, /* tuner slow mode */
{ /* current channel (all 0) */
0UL /* channel.frequency */
DRX_STANDARD_UNKNOWN, /* current standard */
DRX_STANDARD_UNKNOWN, /* previous standard */
DRX_STANDARD_UNKNOWN, /* diCacheStandard */
- FALSE, /* useBootloader */
+ false, /* useBootloader */
0UL, /* capabilities */
0 /* mfx */
};
*
*/
DRXAudData_t DRXJDefaultAudData_g = {
- FALSE, /* audioIsActive */
+ false, /* audioIsActive */
DRX_AUD_STANDARD_AUTO, /* audioStandard */
/* i2sdata */
{
- FALSE, /* outputEnable */
+ false, /* outputEnable */
48000, /* frequency */
DRX_I2S_MODE_MASTER, /* mode */
DRX_I2S_WORDLENGTH_32, /* wordLength */
},
/* volume */
{
- TRUE, /* mute; */
+ true, /* mute; */
0, /* volume */
DRX_AUD_AVC_OFF, /* avcMode */
0, /* avcRefLevel */
DRX_AUD_FM_DEEMPH_75US, /* deemph */
DRX_BTSC_STEREO, /* btscDetect */
0, /* rdsDataCounter */
- FALSE /* rdsDataPresent */
+ false /* rdsDataPresent */
};
/*-----------------------------------------------------------------------------
static DRXStatus_t PowerDownAud(pDRXDemodInstance_t demod);
#ifndef DRXJ_DIGITAL_ONLY
-static DRXStatus_t PowerUpAud(pDRXDemodInstance_t demod, Bool_t setStandard);
+static DRXStatus_t PowerUpAud(pDRXDemodInstance_t demod, bool setStandard);
#endif
static DRXStatus_t
static DRXStatus_t
CtrlUCodeUpload(pDRXDemodInstance_t demod,
pDRXUCodeInfo_t mcInfo,
- DRXUCodeAction_t action, Bool_t audioMCUpload);
+ DRXUCodeAction_t action, bool audioMCUpload);
#endif /* DRXJ_SPLIT_UCODE_UPLOAD */
/*============================================================================*/
TODO: check ignoring single/multimaster is ok for AUD access ?
*/
-#define DRXJ_ISAUDWRITE( addr ) (((((addr)>>16)&1)==1)?TRUE:FALSE)
+#define DRXJ_ISAUDWRITE( addr ) (((((addr)>>16)&1)==1)?true:false)
#define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */
/*============================================================================*/
/**
-* \fn Bool_t IsHandledByAudTrIf( DRXaddr_t addr )
+* \fn bool IsHandledByAudTrIf( DRXaddr_t addr )
* \brief Check if this address is handled by the audio token ring interface.
* \param addr
-* \return Bool_t
-* \retval TRUE Yes, handled by audio token ring interface
-* \retval FALSE No, not handled by audio token ring interface
+* \return bool
+* \retval true Yes, handled by audio token ring interface
+* \retval false No, not handled by audio token ring interface
*
*/
static
-Bool_t IsHandledByAudTrIf(DRXaddr_t addr)
+bool IsHandledByAudTrIf(DRXaddr_t addr)
{
- Bool_t retval = FALSE;
+ bool retval = false;
if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) &&
(DRXDAP_FASI_ADDR2BANK(addr) > 1) &&
(DRXDAP_FASI_ADDR2BANK(addr) < 6)) {
- retval = TRUE;
+ retval = true;
}
return (retval);
DRXStatus_t DRXJ_DAP_AtomicReadWriteBlock(struct i2c_device_addr *devAddr,
DRXaddr_t addr,
u16 datasize,
- u8 *data, Bool_t readFlag)
+ u8 *data, bool readFlag)
{
DRXJHiCmd_t hiCmd;
hiCmd.param2 =
(u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START);
hiCmd.param3 = (u16) ((datasize / 2) - 1);
- if (readFlag == FALSE) {
+ if (readFlag == false) {
hiCmd.param3 |= DRXJ_HI_ATOMIC_WRITE;
} else {
hiCmd.param3 |= DRXJ_HI_ATOMIC_READ;
DRXDAP_FASI_ADDR2BANK(addr));
hiCmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr);
- if (readFlag == FALSE) {
+ if (readFlag == false) {
/* write data to buffer */
for (i = 0; i < (datasize / 2); i++) {
CHK_ERROR(HICommand(devAddr, &hiCmd, &dummy));
- if (readFlag == TRUE) {
+ if (readFlag == true) {
/* read data from buffer */
for (i = 0; i < (datasize / 2); i++) {
DRXJ_DAP_ReadReg16(devAddr,
}
rc = DRXJ_DAP_AtomicReadWriteBlock(devAddr, addr,
- sizeof(*data), buf, TRUE);
+ sizeof(*data), buf, true);
word = (u32) buf[3];
word <<= 8;
{
u16 waitCmd = 0;
u16 nrRetries = 0;
- Bool_t powerdown_cmd = FALSE;
+ bool powerdown_cmd = false;
/* Write parameters */
switch (cmd->cmd) {
}
/* Detect power down to ommit reading result */
- powerdown_cmd = (Bool_t) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
+ powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
(((cmd->
param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M)
== SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
- if (powerdown_cmd == FALSE) {
+ if (powerdown_cmd == false) {
/* Wait until command rdy */
do {
nrRetries++;
RR16(devAddr, SIO_HI_RA_RAM_RES__A, result);
}
- /* if ( powerdown_cmd == TRUE ) */
+ /* if ( powerdown_cmd == true ) */
return (DRX_STS_OK);
rw_error:
return (DRX_STS_ERROR);
bid = (bid >> 10) & 0xf;
WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE);
- extAttr->hasLNA = TRUE;
- extAttr->hasNTSC = FALSE;
- extAttr->hasBTSC = FALSE;
- extAttr->hasOOB = FALSE;
- extAttr->hasSMATX = TRUE;
- extAttr->hasSMARX = FALSE;
- extAttr->hasGPIO = FALSE;
- extAttr->hasIRQN = FALSE;
+ extAttr->hasLNA = true;
+ extAttr->hasNTSC = false;
+ extAttr->hasBTSC = false;
+ extAttr->hasOOB = false;
+ extAttr->hasSMATX = true;
+ extAttr->hasSMARX = false;
+ extAttr->hasGPIO = false;
+ extAttr->hasIRQN = false;
break;
case 0x33:
- extAttr->hasLNA = FALSE;
- extAttr->hasNTSC = FALSE;
- extAttr->hasBTSC = FALSE;
- extAttr->hasOOB = FALSE;
- extAttr->hasSMATX = TRUE;
- extAttr->hasSMARX = FALSE;
- extAttr->hasGPIO = FALSE;
- extAttr->hasIRQN = FALSE;
+ extAttr->hasLNA = false;
+ extAttr->hasNTSC = false;
+ extAttr->hasBTSC = false;
+ extAttr->hasOOB = false;
+ extAttr->hasSMATX = true;
+ extAttr->hasSMARX = false;
+ extAttr->hasGPIO = false;
+ extAttr->hasIRQN = false;
break;
case 0x45:
- extAttr->hasLNA = TRUE;
- extAttr->hasNTSC = TRUE;
- extAttr->hasBTSC = FALSE;
- extAttr->hasOOB = FALSE;
- extAttr->hasSMATX = TRUE;
- extAttr->hasSMARX = TRUE;
- extAttr->hasGPIO = TRUE;
- extAttr->hasIRQN = FALSE;
+ extAttr->hasLNA = true;
+ extAttr->hasNTSC = true;
+ extAttr->hasBTSC = false;
+ extAttr->hasOOB = false;
+ extAttr->hasSMATX = true;
+ extAttr->hasSMARX = true;
+ extAttr->hasGPIO = true;
+ extAttr->hasIRQN = false;
break;
case 0x46:
- extAttr->hasLNA = FALSE;
- extAttr->hasNTSC = TRUE;
- extAttr->hasBTSC = FALSE;
- extAttr->hasOOB = FALSE;
- extAttr->hasSMATX = TRUE;
- extAttr->hasSMARX = TRUE;
- extAttr->hasGPIO = TRUE;
- extAttr->hasIRQN = FALSE;
+ extAttr->hasLNA = false;
+ extAttr->hasNTSC = true;
+ extAttr->hasBTSC = false;
+ extAttr->hasOOB = false;
+ extAttr->hasSMATX = true;
+ extAttr->hasSMARX = true;
+ extAttr->hasGPIO = true;
+ extAttr->hasIRQN = false;
break;
case 0x41:
- extAttr->hasLNA = TRUE;
- extAttr->hasNTSC = TRUE;
- extAttr->hasBTSC = TRUE;
- extAttr->hasOOB = FALSE;
- extAttr->hasSMATX = TRUE;
- extAttr->hasSMARX = TRUE;
- extAttr->hasGPIO = TRUE;
- extAttr->hasIRQN = FALSE;
+ extAttr->hasLNA = true;
+ extAttr->hasNTSC = true;
+ extAttr->hasBTSC = true;
+ extAttr->hasOOB = false;
+ extAttr->hasSMATX = true;
+ extAttr->hasSMARX = true;
+ extAttr->hasGPIO = true;
+ extAttr->hasIRQN = false;
break;
case 0x43:
- extAttr->hasLNA = FALSE;
- extAttr->hasNTSC = TRUE;
- extAttr->hasBTSC = TRUE;
- extAttr->hasOOB = FALSE;
- extAttr->hasSMATX = TRUE;
- extAttr->hasSMARX = TRUE;
- extAttr->hasGPIO = TRUE;
- extAttr->hasIRQN = FALSE;
+ extAttr->hasLNA = false;
+ extAttr->hasNTSC = true;
+ extAttr->hasBTSC = true;
+ extAttr->hasOOB = false;
+ extAttr->hasSMATX = true;
+ extAttr->hasSMARX = true;
+ extAttr->hasGPIO = true;
+ extAttr->hasIRQN = false;
break;
case 0x32:
- extAttr->hasLNA = TRUE;
- extAttr->hasNTSC = FALSE;
- extAttr->hasBTSC = FALSE;
- extAttr->hasOOB = TRUE;
- extAttr->hasSMATX = TRUE;
- extAttr->hasSMARX = TRUE;
- extAttr->hasGPIO = TRUE;
- extAttr->hasIRQN = TRUE;
+ extAttr->hasLNA = true;
+ extAttr->hasNTSC = false;
+ extAttr->hasBTSC = false;
+ extAttr->hasOOB = true;
+ extAttr->hasSMATX = true;
+ extAttr->hasSMARX = true;
+ extAttr->hasGPIO = true;
+ extAttr->hasIRQN = true;
break;
case 0x34:
- extAttr->hasLNA = FALSE;
- extAttr->hasNTSC = TRUE;
- extAttr->hasBTSC = TRUE;
- extAttr->hasOOB = TRUE;
- extAttr->hasSMATX = TRUE;
- extAttr->hasSMARX = TRUE;
- extAttr->hasGPIO = TRUE;
- extAttr->hasIRQN = TRUE;
+ extAttr->hasLNA = false;
+ extAttr->hasNTSC = true;
+ extAttr->hasBTSC = true;
+ extAttr->hasOOB = true;
+ extAttr->hasSMATX = true;
+ extAttr->hasSMARX = true;
+ extAttr->hasGPIO = true;
+ extAttr->hasIRQN = true;
break;
case 0x42:
- extAttr->hasLNA = TRUE;
- extAttr->hasNTSC = TRUE;
- extAttr->hasBTSC = TRUE;
- extAttr->hasOOB = TRUE;
- extAttr->hasSMATX = TRUE;
- extAttr->hasSMARX = TRUE;
- extAttr->hasGPIO = TRUE;
- extAttr->hasIRQN = TRUE;
+ extAttr->hasLNA = true;
+ extAttr->hasNTSC = true;
+ extAttr->hasBTSC = true;
+ extAttr->hasOOB = true;
+ extAttr->hasSMATX = true;
+ extAttr->hasSMARX = true;
+ extAttr->hasGPIO = true;
+ extAttr->hasIRQN = true;
break;
case 0x44:
- extAttr->hasLNA = FALSE;
- extAttr->hasNTSC = TRUE;
- extAttr->hasBTSC = TRUE;
- extAttr->hasOOB = TRUE;
- extAttr->hasSMATX = TRUE;
- extAttr->hasSMARX = TRUE;
- extAttr->hasGPIO = TRUE;
- extAttr->hasIRQN = TRUE;
+ extAttr->hasLNA = false;
+ extAttr->hasNTSC = true;
+ extAttr->hasBTSC = true;
+ extAttr->hasOOB = true;
+ extAttr->hasSMATX = true;
+ extAttr->hasSMARX = true;
+ extAttr->hasGPIO = true;
+ extAttr->hasIRQN = true;
break;
default:
/* Unknown device variant */
extAttr = (pDRXJData_t) demod->myExtAttr;
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
- if (cfgData->enableMPEGOutput == TRUE) {
+ if (cfgData->enableMPEGOutput == true) {
/* quick and dirty patch to set MPEG incase current std is not
producing MPEG */
switch (extAttr->standard) {
FEC_OC_AVR_PARM_A__PRE);
WR16(devAddr, FEC_OC_AVR_PARM_B__A,
FEC_OC_AVR_PARM_B__PRE);
- if (cfgData->staticCLK == TRUE) {
+ if (cfgData->staticCLK == true) {
WR16(devAddr, FEC_OC_RCN_GAIN__A, 0xD);
} else {
WR16(devAddr, FEC_OC_RCN_GAIN__A,
/* Check insertion of the Reed-Solomon parity bytes */
RR16(devAddr, FEC_OC_MODE__A, &fecOcRegMode);
RR16(devAddr, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
- if (cfgData->insertRSByte == TRUE) {
+ if (cfgData->insertRSByte == true) {
/* enable parity symbol forward */
fecOcRegMode |= FEC_OC_MODE_PARITY__M;
/* MVAL disable during parity bytes */
break;
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_C:
- /* insertRSByte = TRUE -> coef = 188/188 -> 1, RS bits are in MPEG output */
+ /* insertRSByte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */
rcnRate =
(Frac28
(maxBitRate,
default:
return (DRX_STS_ERROR);
} /* extAttr->standard */
- } else { /* insertRSByte == FALSE */
+ } else { /* insertRSByte == false */
/* disable parity symbol forward */
fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
break;
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_C:
- /* insertRSByte = FALSE -> coef = 188/204, RS bits not in MPEG output */
+ /* insertRSByte = false -> coef = 188/204, RS bits not in MPEG output */
rcnRate =
(Frac28
(maxBitRate,
} /* extAttr->standard */
}
- if (cfgData->enableParallel == TRUE) { /* MPEG data output is paralel -> clear ipr_mode[0] */
+ if (cfgData->enableParallel == true) { /* MPEG data output is paralel -> clear ipr_mode[0] */
fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
} else { /* MPEG data output is serial -> set ipr_mode[0] */
fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
}
/* Control slective inversion of output bits */
- if (cfgData->invertDATA == TRUE) {
+ if (cfgData->invertDATA == true) {
fecOcRegIprInvert |= InvertDataMask;
} else {
fecOcRegIprInvert &= (~(InvertDataMask));
}
- if (cfgData->invertERR == TRUE) {
+ if (cfgData->invertERR == true) {
fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
} else {
fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
}
- if (cfgData->invertSTR == TRUE) {
+ if (cfgData->invertSTR == true) {
fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
} else {
fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
}
- if (cfgData->invertVAL == TRUE) {
+ if (cfgData->invertVAL == true) {
fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
} else {
fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
}
- if (cfgData->invertCLK == TRUE) {
+ if (cfgData->invertCLK == true) {
fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
} else {
fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
}
- if (cfgData->staticCLK == TRUE) { /* Static mode */
+ if (cfgData->staticCLK == true) { /* Static mode */
u32 dtoRate = 0;
u32 bitRate = 0;
u16 fecOcDtoBurstLen = 0;
switch (extAttr->standard) {
case DRX_STANDARD_8VSB:
fecOcDtoPeriod = 4;
- if (cfgData->insertRSByte == TRUE) {
+ if (cfgData->insertRSByte == true) {
fecOcDtoBurstLen = 208;
}
break;
case DRX_STANDARD_ITU_A:
{
u32 symbolRateTh = 6400000;
- if (cfgData->insertRSByte == TRUE) {
+ if (cfgData->insertRSByte == true) {
fecOcDtoBurstLen = 204;
symbolRateTh = 5900000;
}
break;
case DRX_STANDARD_ITU_B:
fecOcDtoPeriod = 1;
- if (cfgData->insertRSByte == TRUE) {
+ if (cfgData->insertRSByte == true) {
fecOcDtoBurstLen = 128;
}
break;
case DRX_STANDARD_ITU_C:
fecOcDtoPeriod = 1;
- if (cfgData->insertRSByte == TRUE) {
+ if (cfgData->insertRSByte == true) {
fecOcDtoBurstLen = 204;
}
break;
MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH <<
SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B;
WR16(devAddr, SIO_PDR_MD0_CFG__A, sioPdrMdCfg);
- if (cfgData->enableParallel == TRUE) { /* MPEG data output is paralel -> set MD1 to MD7 to output mode */
+ if (cfgData->enableParallel == true) { /* MPEG data output is paralel -> set MD1 to MD7 to output mode */
sioPdrMdCfg =
MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH <<
SIO_PDR_MD0_CFG_DRIVE__B | 0x03 <<
FEC_OC_SNC_MODE_CORR_DISABLE__M));
fecOcEmsMode &= (~FEC_OC_EMS_MODE_MODE__M);
- if (extAttr->disableTEIhandling == TRUE) {
+ if (extAttr->disableTEIhandling == true) {
/* do not change TEI bit */
fecOcDprMode |= FEC_OC_DPR_MODE_ERR_DISABLE__M;
fecOcSncMode |= FEC_OC_SNC_MODE_CORR_DISABLE__M |
/* reset to default (normal bit order) */
fecOcIprMode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M);
- if (extAttr->bitReverseMpegOutout == TRUE) {
+ if (extAttr->bitReverseMpegOutout == true) {
/* reverse bit order */
fecOcIprMode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M;
}
extAttr = (pDRXJData_t) demod->myExtAttr;
commonAttr = demod->myCommonAttr;
- if ((commonAttr->mpegCfg.staticCLK == TRUE)
- && (commonAttr->mpegCfg.enableParallel == FALSE)) {
+ if ((commonAttr->mpegCfg.staticCLK == true)
+ && (commonAttr->mpegCfg.enableParallel == false)) {
RR16(devAddr, FEC_OC_COMM_MB__A, &fecOcCommMb);
fecOcCommMb &= ~FEC_OC_COMM_MB_CTL_ON;
if (extAttr->mpegStartWidth == DRXJ_MPEG_START_WIDTH_8CLKCYC) {
Set disable TEI bit handling flag.
TEI must be left untouched by device in case of BER measurements using
external equipment that is unable to ignore the TEI bit in the TS.
- Default will FALSE (enable TEI bit handling).
- Reverse output bit order. Default is FALSE (msb on MD7 (parallel) or out first (serial)).
+ Default will false (enable TEI bit handling).
+ Reverse output bit order. Default is false (msb on MD7 (parallel) or out first (serial)).
Set clock rate. Default is auto that is derived from symbol rate.
The flags and values will also be used to set registers during a set channel.
*/
/*====================================================================*/
case DRX_UIO1:
/* DRX_UIO1: SMA_TX UIO-1 */
- if (extAttr->hasSMATX != TRUE)
+ if (extAttr->hasSMATX != true)
return DRX_STS_ERROR;
switch (UIOCfg->mode) {
case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */
/*====================================================================*/
case DRX_UIO2:
/* DRX_UIO2: SMA_RX UIO-2 */
- if (extAttr->hasSMARX != TRUE)
+ if (extAttr->hasSMARX != true)
return DRX_STS_ERROR;
switch (UIOCfg->mode) {
case DRX_UIO_MODE_FIRMWARE0: /* falltrough */
/*====================================================================*/
case DRX_UIO3:
/* DRX_UIO3: GPIO UIO-3 */
- if (extAttr->hasGPIO != TRUE)
+ if (extAttr->hasGPIO != true)
return DRX_STS_ERROR;
switch (UIOCfg->mode) {
case DRX_UIO_MODE_FIRMWARE0: /* falltrough */
/*====================================================================*/
case DRX_UIO4:
/* DRX_UIO4: IRQN UIO-4 */
- if (extAttr->hasIRQN != TRUE)
+ if (extAttr->hasIRQN != true)
return DRX_STS_ERROR;
switch (UIOCfg->mode) {
case DRX_UIO_MODE_READWRITE:
pDRXJData_t extAttr = (pDRXJData_t) NULL;
pDRXUIOMode_t UIOMode[4] = { NULL };
- pBool_t UIOAvailable[4] = { NULL };
+ bool * UIOAvailable[4] = { NULL };
extAttr = demod->myExtAttr;
return DRX_STS_INVALID_ARG;
}
- if (*UIOAvailable[UIOCfg->uio] == FALSE) {
+ if (*UIOAvailable[UIOCfg->uio] == false) {
return DRX_STS_ERROR;
}
/*====================================================================*/
case DRX_UIO1:
/* DRX_UIO1: SMA_TX UIO-1 */
- if (extAttr->hasSMATX != TRUE)
+ if (extAttr->hasSMATX != true)
return DRX_STS_ERROR;
if ((extAttr->uioSmaTxMode != DRX_UIO_MODE_READWRITE)
&& (extAttr->uioSmaTxMode != DRX_UIO_MODE_FIRMWARE_SAW)) {
/* use corresponding bit in io data output registar */
RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value);
- if (UIOData->value == FALSE) {
+ if (UIOData->value == false) {
value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
} else {
value |= 0x8000; /* write one to 15th bit - 1st UIO */
/*======================================================================*/
case DRX_UIO2:
/* DRX_UIO2: SMA_RX UIO-2 */
- if (extAttr->hasSMARX != TRUE)
+ if (extAttr->hasSMARX != true)
return DRX_STS_ERROR;
if (extAttr->uioSmaRxMode != DRX_UIO_MODE_READWRITE) {
return DRX_STS_ERROR;
/* use corresponding bit in io data output registar */
RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value);
- if (UIOData->value == FALSE) {
+ if (UIOData->value == false) {
value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */
} else {
value |= 0x4000; /* write one to 14th bit - 2nd UIO */
/*====================================================================*/
case DRX_UIO3:
/* DRX_UIO3: ASEL UIO-3 */
- if (extAttr->hasGPIO != TRUE)
+ if (extAttr->hasGPIO != true)
return DRX_STS_ERROR;
if (extAttr->uioGPIOMode != DRX_UIO_MODE_READWRITE) {
return DRX_STS_ERROR;
/* use corresponding bit in io data output registar */
RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_HI__A, &value);
- if (UIOData->value == FALSE) {
+ if (UIOData->value == false) {
value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
} else {
value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
/*=====================================================================*/
case DRX_UIO4:
/* DRX_UIO4: IRQN UIO-4 */
- if (extAttr->hasIRQN != TRUE)
+ if (extAttr->hasIRQN != true)
return DRX_STS_ERROR;
if (extAttr->uioIRQNMode != DRX_UIO_MODE_READWRITE) {
/* use corresponding bit in io data output registar */
RR16(demod->myI2CDevAddr, SIO_PDR_UIO_OUT_LO__A, &value);
- if (UIOData->value == FALSE) {
+ if (UIOData->value == false) {
value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */
} else {
value |= 0x1000; /* write one to 12th bit - 4th UIO */
/*====================================================================*/
case DRX_UIO1:
/* DRX_UIO1: SMA_TX UIO-1 */
- if (extAttr->hasSMATX != TRUE)
+ if (extAttr->hasSMATX != true)
return DRX_STS_ERROR;
if (extAttr->uioSmaTxMode != DRX_UIO_MODE_READWRITE) {
RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value);
if ((value & 0x8000) != 0) { /* check 15th bit - 1st UIO */
- UIOData->value = TRUE;
+ UIOData->value = true;
} else {
- UIOData->value = FALSE;
+ UIOData->value = false;
}
break;
/*======================================================================*/
case DRX_UIO2:
/* DRX_UIO2: SMA_RX UIO-2 */
- if (extAttr->hasSMARX != TRUE)
+ if (extAttr->hasSMARX != true)
return DRX_STS_ERROR;
if (extAttr->uioSmaRxMode != DRX_UIO_MODE_READWRITE) {
RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value);
if ((value & 0x4000) != 0) { /* check 14th bit - 2nd UIO */
- UIOData->value = TRUE;
+ UIOData->value = true;
} else {
- UIOData->value = FALSE;
+ UIOData->value = false;
}
break;
/*=====================================================================*/
case DRX_UIO3:
/* DRX_UIO3: GPIO UIO-3 */
- if (extAttr->hasGPIO != TRUE)
+ if (extAttr->hasGPIO != true)
return DRX_STS_ERROR;
if (extAttr->uioGPIOMode != DRX_UIO_MODE_READWRITE) {
/* read io input data registar */
RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_HI__A, &value);
if ((value & 0x0004) != 0) { /* check 2nd bit - 3rd UIO */
- UIOData->value = TRUE;
+ UIOData->value = true;
} else {
- UIOData->value = FALSE;
+ UIOData->value = false;
}
break;
/*=====================================================================*/
case DRX_UIO4:
/* DRX_UIO4: IRQN UIO-4 */
- if (extAttr->hasIRQN != TRUE)
+ if (extAttr->hasIRQN != true)
return DRX_STS_ERROR;
if (extAttr->uioIRQNMode != DRX_UIO_MODE_READWRITE) {
/* read io input data registar */
RR16(demod->myI2CDevAddr, SIO_PDR_UIO_IN_LO__A, &value);
if ((value & 0x1000) != 0) { /* check 12th bit - 4th UIO */
- UIOData->value = TRUE;
+ UIOData->value = true;
} else {
- UIOData->value = FALSE;
+ UIOData->value = false;
}
break;
/*====================================================================*/
*/
static DRXStatus_t
-CtrlI2CBridge(pDRXDemodInstance_t demod, pBool_t bridgeClosed)
+CtrlI2CBridge(pDRXDemodInstance_t demod, bool * bridgeClosed)
{
DRXJHiCmd_t hiCmd;
u16 result = 0;
hiCmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL;
hiCmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
- if (*bridgeClosed == TRUE) {
+ if (*bridgeClosed == true) {
hiCmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED;
} else {
hiCmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN;
struct i2c_device_addr *devAddr = NULL;
u16 data = 0;
u32 startTime = 0;
- static Bool_t bitInverted = FALSE;
+ static bool bitInverted = false;
devAddr = demod->myI2CDevAddr;
extAttr = (pDRXJData_t) demod->myExtAttr;
#define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2)
static
DRXStatus_t DRXJ_DAP_SCU_AtomicReadWriteBlock(struct i2c_device_addr *devAddr, DRXaddr_t addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */
- u8 *data, Bool_t readFlag)
+ u8 *data, bool readFlag)
{
DRXJSCUCmd_t scuCmd;
u16 setParamParameters[15];
scuCmd.parameter = setParamParameters;
CHK_ERROR(SCUCommand(devAddr, &scuCmd));
- if (readFlag == TRUE) {
+ if (readFlag == true) {
int i = 0;
/* read data from buffer */
for (i = 0; i < (datasize / 2); i++) {
return DRX_STS_INVALID_ARG;
}
- rc = DRXJ_DAP_SCU_AtomicReadWriteBlock(devAddr, addr, 2, buf, TRUE);
+ rc = DRXJ_DAP_SCU_AtomicReadWriteBlock(devAddr, addr, 2, buf, true);
word = (u16) (buf[0] + (buf[1] << 8));
buf[0] = (u8) (data & 0xff);
buf[1] = (u8) ((data >> 8) & 0xff);
- rc = DRXJ_DAP_SCU_AtomicReadWriteBlock(devAddr, addr, 2, buf, FALSE);
+ rc = DRXJ_DAP_SCU_AtomicReadWriteBlock(devAddr, addr, 2, buf, false);
return rc;
}
* \param active
* \return DRXStatus_t.
*/
-static DRXStatus_t IQMSetAf(pDRXDemodInstance_t demod, Bool_t active)
+static DRXStatus_t IQMSetAf(pDRXDemodInstance_t demod, bool active)
{
u16 data = 0;
struct i2c_device_addr *devAddr = NULL;
/**
* \brief set configuration of pin-safe mode
* \param demod instance of demodulator.
-* \param enable boolean; TRUE: activate pin-safe mode, FALSE: de-activate p.s.m.
+* \param enable boolean; true: activate pin-safe mode, false: de-activate p.s.m.
* \return DRXStatus_t.
*/
static DRXStatus_t
-CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, pBool_t enable)
+CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool * enable)
{
pDRXJData_t extAttr = (pDRXJData_t) NULL;
struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL;
/* Write magic word to enable pdr reg write */
WR16(devAddr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
- if (*enable == TRUE) {
- Bool_t bridgeEnabled = FALSE;
+ if (*enable == true) {
+ bool bridgeEnabled = false;
/* MPEG pins to input */
WR16(devAddr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE);
/* PD_RF_AGC Analog DAC outputs, cannot be set to input or tristate!
PD_IF_AGC Analog DAC outputs, cannot be set to input or tristate! */
- CHK_ERROR(IQMSetAf(demod, FALSE));
+ CHK_ERROR(IQMSetAf(demod, false));
/* PD_CVBS Analog DAC output, standby mode
PD_SIF Analog DAC output, standby mode */
* \return DRXStatus_t.
*/
static DRXStatus_t
-CtrlGetCfgPdrSafeMode(pDRXDemodInstance_t demod, pBool_t enabled)
+CtrlGetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool * enabled)
{
pDRXJData_t extAttr = (pDRXJData_t) NULL;
WR16(devAddr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
agcRf = 0x800 + pAgcRfSettings->cutOffCurrent;
- if (commonAttr->tunerRfAgcPol == TRUE) {
+ if (commonAttr->tunerRfAgcPol == true) {
agcRf = 0x87ff - agcRf;
}
agcIf = 0x800;
- if (commonAttr->tunerIfAgcPol == TRUE) {
+ if (commonAttr->tunerIfAgcPol == true) {
agcRf = 0x87ff - agcRf;
}
*/
static DRXStatus_t
SetFrequency(pDRXDemodInstance_t demod,
- pDRXChannel_t channel, DRXFrequency_t tunerFreqOffset)
+ pDRXChannel_t channel, s32 tunerFreqOffset)
{
struct i2c_device_addr *devAddr = NULL;
pDRXCommonAttr_t commonAttr = NULL;
- DRXFrequency_t samplingFrequency = 0;
- DRXFrequency_t frequencyShift = 0;
- DRXFrequency_t ifFreqActual = 0;
- DRXFrequency_t rfFreqResidual = 0;
- DRXFrequency_t adcFreq = 0;
- DRXFrequency_t intermediateFreq = 0;
+ s32 samplingFrequency = 0;
+ s32 frequencyShift = 0;
+ s32 ifFreqActual = 0;
+ s32 rfFreqResidual = 0;
+ s32 adcFreq = 0;
+ s32 intermediateFreq = 0;
u32 iqmFsRateOfs = 0;
pDRXJData_t extAttr = NULL;
- Bool_t adcFlip = TRUE;
- Bool_t selectPosImage = FALSE;
- Bool_t rfMirror = FALSE;
- Bool_t tunerMirror = TRUE;
- Bool_t imageToSelect = TRUE;
- DRXFrequency_t fmFrequencyShift = 0;
+ bool adcFlip = true;
+ bool selectPosImage = false;
+ bool rfMirror = false;
+ bool tunerMirror = true;
+ bool imageToSelect = true;
+ s32 fmFrequencyShift = 0;
devAddr = demod->myI2CDevAddr;
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
extAttr = (pDRXJData_t) demod->myExtAttr;
rfFreqResidual = -1 * tunerFreqOffset;
- rfMirror = (extAttr->mirror == DRX_MIRROR_YES) ? TRUE : FALSE;
- tunerMirror = demod->myCommonAttr->mirrorFreqSpect ? FALSE : TRUE;
+ rfMirror = (extAttr->mirror == DRX_MIRROR_YES) ? true : false;
+ tunerMirror = demod->myCommonAttr->mirrorFreqSpect ? false : true;
/*
Program frequency shifter
No need to account for mirroring on RF
case DRX_STANDARD_ITU_C: /* fallthrough */
case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */
case DRX_STANDARD_8VSB:
- selectPosImage = TRUE;
+ selectPosImage = true;
break;
case DRX_STANDARD_FM:
/* After IQM FS sound carrier must appear at 4 Mhz in spect.
case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */
case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */
case DRX_STANDARD_PAL_SECAM_L:
- selectPosImage = FALSE;
+ selectPosImage = false;
break;
default:
return (DRX_STS_INVALID_ARG);
}
intermediateFreq = demod->myCommonAttr->intermediateFreq;
samplingFrequency = demod->myCommonAttr->sysClockFreq / 3;
- if (tunerMirror == TRUE) {
+ if (tunerMirror == true) {
/* tuner doesn't mirror */
ifFreqActual =
intermediateFreq + rfFreqResidual + fmFrequencyShift;
if (ifFreqActual > samplingFrequency / 2) {
/* adc mirrors */
adcFreq = samplingFrequency - ifFreqActual;
- adcFlip = TRUE;
+ adcFlip = true;
} else {
/* adc doesn't mirror */
adcFreq = ifFreqActual;
- adcFlip = FALSE;
+ adcFlip = false;
}
frequencyShift = adcFreq;
imageToSelect =
- (Bool_t) (rfMirror ^ tunerMirror ^ adcFlip ^ selectPosImage);
+ (bool) (rfMirror ^ tunerMirror ^ adcFlip ^ selectPosImage);
iqmFsRateOfs = Frac28(frequencyShift, samplingFrequency);
if (imageToSelect)
/* frequencyShift += tunerFreqOffset; TODO */
WR32(devAddr, IQM_FS_RATE_OFS_LO__A, iqmFsRateOfs);
extAttr->iqmFsRateOfs = iqmFsRateOfs;
- extAttr->posImage = (Bool_t) (rfMirror ^ tunerMirror ^ selectPosImage);
+ extAttr->posImage = (bool) (rfMirror ^ tunerMirror ^ selectPosImage);
return (DRX_STS_OK);
rw_error:
devAddr = demod->myI2CDevAddr;
RR16(devAddr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data);
- if (extAttr->resetPktErrAcc == TRUE) {
+ if (extAttr->resetPktErrAcc == true) {
lastPktErr = data;
pktErr = 0;
- extAttr->resetPktErrAcc = FALSE;
+ extAttr->resetPktErrAcc = false;
}
if (data < lastPktErr) {
u16 packetError = 0;
extAttr = (pDRXJData_t) demod->myExtAttr;
- extAttr->resetPktErrAcc = TRUE;
+ extAttr->resetPktErrAcc = true;
/* call to reset counter */
CHK_ERROR(GetAccPktErr(demod, &packetError));
*/
static DRXStatus_t GetCTLFreqOffset(pDRXDemodInstance_t demod, s32 *CTLFreq)
{
- DRXFrequency_t samplingFrequency = 0;
+ s32 samplingFrequency = 0;
s32 currentFrequency = 0;
s32 nominalFrequency = 0;
s32 carrierFrequencyShift = 0;
nominalFrequency = extAttr->iqmFsRateOfs;
ARR32(devAddr, IQM_FS_RATE_LO__A, (u32 *) & currentFrequency);
- if (extAttr->posImage == TRUE) {
+ if (extAttr->posImage == true) {
/* negative image */
carrierFrequencyShift = nominalFrequency - currentFrequency;
} else {
* \return DRXStatus_t.
*/
static DRXStatus_t
-SetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic)
+SetAgcRf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, bool atomic)
{
struct i2c_device_addr *devAddr = NULL;
pDRXJData_t extAttr = NULL;
* \return DRXStatus_t.
*/
static DRXStatus_t
-SetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, Bool_t atomic)
+SetAgcIf(pDRXDemodInstance_t demod, pDRXJCfgAgc_t agcSettings, bool atomic)
{
struct i2c_device_addr *devAddr = NULL;
pDRXJData_t extAttr = NULL;
* \param active
* \return DRXStatus_t.
*/
-static DRXStatus_t SetIqmAf(pDRXDemodInstance_t demod, Bool_t active)
+static DRXStatus_t SetIqmAf(pDRXDemodInstance_t demod, bool active)
{
u16 data = 0;
struct i2c_device_addr *devAddr = NULL;
* \param channel pointer to channel data.
* \return DRXStatus_t.
*/
-static DRXStatus_t PowerDownVSB(pDRXDemodInstance_t demod, Bool_t primary)
+static DRXStatus_t PowerDownVSB(pDRXDemodInstance_t demod, bool primary)
{
struct i2c_device_addr *devAddr = NULL;
DRXJSCUCmd_t cmdSCU = { /* command */ 0,
/* stop all comm_exec */
WR16(devAddr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
WR16(devAddr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP);
- if (primary == TRUE) {
+ if (primary == true) {
WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP);
- CHK_ERROR(SetIqmAf(demod, FALSE));
+ CHK_ERROR(SetIqmAf(demod, false));
} else {
WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP);
WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP);
WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP);
}
- cfgMPEGOutput.enableMPEGOutput = FALSE;
+ cfgMPEGOutput.enableMPEGOutput = false;
CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput));
return (DRX_STS_OK);
WR16(devAddr, VSB_TOP_CKGN1TRK__A, 128);
/* B-Input to ADC, PGA+filter in standby */
- if (extAttr->hasLNA == FALSE) {
+ if (extAttr->hasLNA == false) {
WR16(devAddr, IQM_AF_AMUX__A, 0x02);
};
/* turn on IQMAF. It has to be in front of setAgc**() */
- CHK_ERROR(SetIqmAf(demod, TRUE));
+ CHK_ERROR(SetIqmAf(demod, true));
CHK_ERROR(ADCSynchronization(demod));
CHK_ERROR(InitAGC(demod));
- CHK_ERROR(SetAgcIf(demod, &(extAttr->vsbIfAgcCfg), FALSE));
- CHK_ERROR(SetAgcRf(demod, &(extAttr->vsbRfAgcCfg), FALSE));
+ CHK_ERROR(SetAgcIf(demod, &(extAttr->vsbIfAgcCfg), false));
+ CHK_ERROR(SetAgcRf(demod, &(extAttr->vsbRfAgcCfg), false));
{
/* TODO fix this, store a DRXJCfgAfeGain_t structure in DRXJData_t instead
of only the gain */
/* TODO: move to setStandard after hardware reset value problem is solved */
/* Configure initial MPEG output */
DRXCfgMPEGOutput_t cfgMPEGOutput;
- cfgMPEGOutput.enableMPEGOutput = TRUE;
+ cfgMPEGOutput.enableMPEGOutput = true;
cfgMPEGOutput.insertRSByte = commonAttr->mpegCfg.insertRSByte;
cfgMPEGOutput.enableParallel =
commonAttr->mpegCfg.enableParallel;
* \param channel pointer to channel data.
* \return DRXStatus_t.
*/
-static DRXStatus_t PowerDownQAM(pDRXDemodInstance_t demod, Bool_t primary)
+static DRXStatus_t PowerDownQAM(pDRXDemodInstance_t demod, bool primary)
{
DRXJSCUCmd_t cmdSCU = { /* command */ 0,
/* parameterLen */ 0,
cmdSCU.result = &cmdResult;
CHK_ERROR(SCUCommand(devAddr, &cmdSCU));
- if (primary == TRUE) {
+ if (primary == true) {
WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP);
- CHK_ERROR(SetIqmAf(demod, FALSE));
+ CHK_ERROR(SetIqmAf(demod, false));
} else {
WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP);
WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP);
WR16(devAddr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP);
}
- cfgMPEGOutput.enableMPEGOutput = FALSE;
+ cfgMPEGOutput.enableMPEGOutput = false;
CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput));
return (DRX_STS_OK);
*/
static DRXStatus_t
SetQAM(pDRXDemodInstance_t demod,
- pDRXChannel_t channel, DRXFrequency_t tunerFreqOffset, u32 op)
+ pDRXChannel_t channel, s32 tunerFreqOffset, u32 op)
{
struct i2c_device_addr *devAddr = NULL;
pDRXJData_t extAttr = NULL;
}
if (op & QAM_SET_OP_ALL) {
- if (extAttr->hasLNA == FALSE) {
+ if (extAttr->hasLNA == false) {
WR16(devAddr, IQM_AF_AMUX__A, 0x02);
}
WR16(devAddr, IQM_CF_SYMMETRIC__A, 0);
/* No more resets of the IQM, current standard correctly set =>
now AGCs can be configured. */
/* turn on IQMAF. It has to be in front of setAgc**() */
- CHK_ERROR(SetIqmAf(demod, TRUE));
+ CHK_ERROR(SetIqmAf(demod, true));
CHK_ERROR(ADCSynchronization(demod));
CHK_ERROR(InitAGC(demod));
- CHK_ERROR(SetAgcIf(demod, &(extAttr->qamIfAgcCfg), FALSE));
- CHK_ERROR(SetAgcRf(demod, &(extAttr->qamRfAgcCfg), FALSE));
+ CHK_ERROR(SetAgcIf(demod, &(extAttr->qamIfAgcCfg), false));
+ CHK_ERROR(SetAgcRf(demod, &(extAttr->qamRfAgcCfg), false));
{
/* TODO fix this, store a DRXJCfgAfeGain_t structure in DRXJData_t instead
of only the gain */
/* Configure initial MPEG output */
DRXCfgMPEGOutput_t cfgMPEGOutput;
- cfgMPEGOutput.enableMPEGOutput = TRUE;
+ cfgMPEGOutput.enableMPEGOutput = true;
cfgMPEGOutput.insertRSByte =
commonAttr->mpegCfg.insertRSByte;
cfgMPEGOutput.enableParallel =
/* flip the spec */
WR32(devAddr, IQM_FS_RATE_OFS_LO__A, iqmFsRateOfs);
extAttr->iqmFsRateOfs = iqmFsRateOfs;
- extAttr->posImage = (extAttr->posImage) ? FALSE : TRUE;
+ extAttr->posImage = (extAttr->posImage) ? false : true;
/* freeze dq/fq updating */
RR16(devAddr, QAM_DQ_MODE__A, &data);
static DRXStatus_t
QAM64Auto(pDRXDemodInstance_t demod,
pDRXChannel_t channel,
- DRXFrequency_t tunerFreqOffset, pDRXLockStatus_t lockStatus)
+ s32 tunerFreqOffset, pDRXLockStatus_t lockStatus)
{
DRXSigQuality_t sigQuality;
u16 data = 0;
static DRXStatus_t
QAM256Auto(pDRXDemodInstance_t demod,
pDRXChannel_t channel,
- DRXFrequency_t tunerFreqOffset, pDRXLockStatus_t lockStatus)
+ s32 tunerFreqOffset, pDRXLockStatus_t lockStatus)
{
DRXSigQuality_t sigQuality;
u32 state = NO_LOCK;
*/
static DRXStatus_t
SetQAMChannel(pDRXDemodInstance_t demod,
- pDRXChannel_t channel, DRXFrequency_t tunerFreqOffset)
+ pDRXChannel_t channel, s32 tunerFreqOffset)
{
DRXLockStatus_t lockStatus = DRX_NOT_LOCKED;
pDRXJData_t extAttr = NULL;
- Bool_t autoFlag = FALSE;
+ bool autoFlag = false;
/* external attributes for storing aquired channel constellation */
extAttr = (pDRXJData_t) demod->myExtAttr;
break;
case DRX_CONSTELLATION_AUTO: /* for channel scan */
if (extAttr->standard == DRX_STANDARD_ITU_B) {
- autoFlag = TRUE;
+ autoFlag = true;
/* try to lock default QAM constellation: QAM64 */
channel->constellation = DRX_CONSTELLATION_QAM256;
extAttr->constellation = DRX_CONSTELLATION_QAM256;
} else if (extAttr->standard == DRX_STANDARD_ITU_C) {
channel->constellation = DRX_CONSTELLATION_QAM64;
extAttr->constellation = DRX_CONSTELLATION_QAM64;
- autoFlag = TRUE;
+ autoFlag = true;
if (channel->mirror == DRX_MIRROR_AUTO) {
extAttr->mirror = DRX_MIRROR_NO;
*
*/
static DRXStatus_t
-AtvUpdateConfig(pDRXDemodInstance_t demod, Bool_t forceUpdate)
+AtvUpdateConfig(pDRXDemodInstance_t demod, bool forceUpdate)
{
struct i2c_device_addr *devAddr = NULL;
pDRXJData_t extAttr = NULL;
extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_OUTPUT;
}
- CHK_ERROR(AtvUpdateConfig(demod, FALSE));
+ CHK_ERROR(AtvUpdateConfig(demod, false));
return (DRX_STS_OK);
rw_error:
extAttr->atvTopEqu3[index] = coef->coef3;
extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_COEF;
- CHK_ERROR(AtvUpdateConfig(demod, FALSE));
+ CHK_ERROR(AtvUpdateConfig(demod, false));
return (DRX_STS_OK);
rw_error:
extAttr->atvCfgChangedFlags |= DRXJ_ATV_CHANGED_NOISE_FLT;
}
- CHK_ERROR(AtvUpdateConfig(demod, FALSE));
+ CHK_ERROR(AtvUpdateConfig(demod, false));
return (DRX_STS_OK);
rw_error:
RR16(demod->myI2CDevAddr, ATV_TOP_STDBY__A, &data);
if (data & ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) {
- outputCfg->enableCVBSOutput = TRUE;
+ outputCfg->enableCVBSOutput = true;
} else {
- outputCfg->enableCVBSOutput = FALSE;
+ outputCfg->enableCVBSOutput = false;
}
if (data & ATV_TOP_STDBY_SIF_STDBY_STANDBY) {
- outputCfg->enableSIFOutput = FALSE;
+ outputCfg->enableSIFOutput = false;
} else {
- outputCfg->enableSIFOutput = TRUE;
+ outputCfg->enableSIFOutput = true;
RR16(demod->myI2CDevAddr, ATV_TOP_AF_SIF_ATT__A, &data);
outputCfg->sifAttenuation = (DRXJSIFAttenuation_t) data;
}
/* ATV NTSC */
WR16(devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_ACTIVE);
/* turn on IQM_AF */
- CHK_ERROR(SetIqmAf(demod, TRUE));
+ CHK_ERROR(SetIqmAf(demod, true));
CHK_ERROR(ADCSynchronization(demod));
WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE);
* Calls audio power down
*/
static DRXStatus_t
-PowerDownATV(pDRXDemodInstance_t demod, DRXStandard_t standard, Bool_t primary)
+PowerDownATV(pDRXDemodInstance_t demod, DRXStandard_t standard, bool primary)
{
struct i2c_device_addr *devAddr = NULL;
DRXJSCUCmd_t cmdSCU = { /* command */ 0,
(~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)));
WR16(devAddr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP);
- if (primary == TRUE) {
+ if (primary == true) {
WR16(devAddr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP);
- CHK_ERROR(SetIqmAf(demod, FALSE));
+ CHK_ERROR(SetIqmAf(demod, false));
} else {
WR16(devAddr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP);
WR16(devAddr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP);
/* Upload only audio microcode */
CHK_ERROR(CtrlUCodeUpload
- (demod, &ucodeInfo, UCODE_UPLOAD, TRUE));
+ (demod, &ucodeInfo, UCODE_UPLOAD, true));
- if (commonAttr->verifyMicrocode == TRUE) {
+ if (commonAttr->verifyMicrocode == true) {
CHK_ERROR(CtrlUCodeUpload
- (demod, &ucodeInfo, UCODE_VERIFY, TRUE));
+ (demod, &ucodeInfo, UCODE_VERIFY, true));
}
/* Prevent uploading audio microcode again */
- extAttr->flagAudMcUploaded = TRUE;
+ extAttr->flagAudMcUploaded = true;
}
#endif /* DRXJ_SPLIT_UCODE_UPLOAD */
WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000);
WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A,
SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN);
- extAttr->phaseCorrectionBypass = FALSE;
- extAttr->enableCVBSOutput = TRUE;
+ extAttr->phaseCorrectionBypass = false;
+ extAttr->enableCVBSOutput = true;
break;
case DRX_STANDARD_FM:
/* FM */
(SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW |
SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM));
WR16(devAddr, IQM_RT_ROT_BP__A, IQM_RT_ROT_BP_ROT_OFF_OFF);
- extAttr->phaseCorrectionBypass = TRUE;
- extAttr->enableCVBSOutput = FALSE;
+ extAttr->phaseCorrectionBypass = true;
+ extAttr->enableCVBSOutput = false;
break;
case DRX_STANDARD_PAL_SECAM_BG:
/* PAL/SECAM B/G */
WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000);
WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A,
SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN);
- extAttr->phaseCorrectionBypass = FALSE;
+ extAttr->phaseCorrectionBypass = false;
extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO;
- extAttr->enableCVBSOutput = TRUE;
+ extAttr->enableCVBSOutput = true;
break;
case DRX_STANDARD_PAL_SECAM_DK:
/* PAL/SECAM D/K */
WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000);
WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A,
SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK);
- extAttr->phaseCorrectionBypass = FALSE;
+ extAttr->phaseCorrectionBypass = false;
extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO;
- extAttr->enableCVBSOutput = TRUE;
+ extAttr->enableCVBSOutput = true;
break;
case DRX_STANDARD_PAL_SECAM_I:
/* PAL/SECAM I */
WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000);
WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A,
SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I);
- extAttr->phaseCorrectionBypass = FALSE;
+ extAttr->phaseCorrectionBypass = false;
extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_AUTO;
- extAttr->enableCVBSOutput = TRUE;
+ extAttr->enableCVBSOutput = true;
break;
case DRX_STANDARD_PAL_SECAM_L:
/* PAL/SECAM L with negative modulation */
WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000);
WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A,
SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP);
- extAttr->phaseCorrectionBypass = FALSE;
+ extAttr->phaseCorrectionBypass = false;
extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_USER;
extAttr->atvIfAgcCfg.outputLevel = extAttr->atvRfAgcCfg.top;
- extAttr->enableCVBSOutput = TRUE;
+ extAttr->enableCVBSOutput = true;
break;
case DRX_STANDARD_PAL_SECAM_LP:
/* PAL/SECAM L with positive modulation */
WR16(devAddr, SCU_RAM_ATV_VID_GAIN_LO__A, 0x0000);
WR16(devAddr, SCU_RAM_ATV_AMS_MAX_REF__A,
SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP);
- extAttr->phaseCorrectionBypass = FALSE;
+ extAttr->phaseCorrectionBypass = false;
extAttr->atvIfAgcCfg.ctrlMode = DRX_AGC_CTRL_USER;
extAttr->atvIfAgcCfg.outputLevel = extAttr->atvRfAgcCfg.top;
- extAttr->enableCVBSOutput = TRUE;
+ extAttr->enableCVBSOutput = true;
break;
default:
return (DRX_STS_ERROR);
}
/* Common initializations FM & NTSC & B/G & D/K & I & L & LP */
- if (extAttr->hasLNA == FALSE) {
+ if (extAttr->hasLNA == false) {
WR16(devAddr, IQM_AF_AMUX__A, 0x01);
}
WR16(devAddr, SCU_RAM_GPIO__A, 0);
/* Override reset values with current shadow settings */
- CHK_ERROR(AtvUpdateConfig(demod, TRUE));
+ CHK_ERROR(AtvUpdateConfig(demod, true));
/* Configure/restore AGC settings */
CHK_ERROR(InitAGC(demod));
- CHK_ERROR(SetAgcIf(demod, &(extAttr->atvIfAgcCfg), FALSE));
- CHK_ERROR(SetAgcRf(demod, &(extAttr->atvRfAgcCfg), FALSE));
+ CHK_ERROR(SetAgcIf(demod, &(extAttr->atvIfAgcCfg), false));
+ CHK_ERROR(SetAgcRf(demod, &(extAttr->atvRfAgcCfg), false));
CHK_ERROR(CtrlSetCfgPreSaw(demod, &(extAttr->atvPreSawCfg)));
/* Set SCU ATV substandard,assuming this doesn't require running ATV block */
*/
static DRXStatus_t
SetATVChannel(pDRXDemodInstance_t demod,
- DRXFrequency_t tunerFreqOffset,
+ s32 tunerFreqOffset,
pDRXChannel_t channel, DRXStandard_t standard)
{
DRXJSCUCmd_t cmdSCU = { /* command */ 0,
cmdSCU.result = &cmdResult;
CHK_ERROR(SCUCommand(devAddr, &cmdSCU));
-/* if ( (extAttr->standard == DRX_STANDARD_FM) && (extAttr->flagSetAUDdone == TRUE) )
+/* if ( (extAttr->standard == DRX_STANDARD_FM) && (extAttr->flagSetAUDdone == true) )
{
- extAttr->detectedRDS = (Bool_t)FALSE;
+ extAttr->detectedRDS = (bool)false;
}*/
return (DRX_STS_OK);
GetATVChannel(pDRXDemodInstance_t demod,
pDRXChannel_t channel, DRXStandard_t standard)
{
- DRXFrequency_t offset = 0;
+ s32 offset = 0;
struct i2c_device_addr *devAddr = NULL;
pDRXJData_t extAttr = NULL;
measuredOffset |= 0xFF80;
}
offset +=
- (DRXFrequency_t) (((s16) measuredOffset) * 10);
+ (s32) (((s16) measuredOffset) * 10);
break;
}
case DRX_STANDARD_PAL_SECAM_LP:
measuredOffset |= 0xFF80;
}
offset -=
- (DRXFrequency_t) (((s16) measuredOffset) * 10);
+ (s32) (((s16) measuredOffset) * 10);
}
break;
case DRX_STANDARD_FM:
* \return DRXStatus_t.
*
*/
-static DRXStatus_t PowerUpAud(pDRXDemodInstance_t demod, Bool_t setStandard)
+static DRXStatus_t PowerUpAud(pDRXDemodInstance_t demod, bool setStandard)
{
DRXAudStandard_t audStandard = DRX_AUD_STANDARD_AUTO;
struct i2c_device_addr *devAddr = NULL;
WR16(devAddr, AUD_TOP_TR_MDE__A, 8);
WR16(devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_ACTIVE);
- if (setStandard == TRUE) {
+ if (setStandard == true) {
CHK_ERROR(AUDCtrlSetStandard(demod, &audStandard));
}
WR16(devAddr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
- extAttr->audData.audioIsActive = FALSE;
+ extAttr->audData.audioIsActive = false;
return DRX_STS_OK;
rw_error:
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
/* Modus register is combined in to RAM location */
}
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
- status->valid = FALSE;
+ status->valid = false;
RR16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &rRDSArrayCntInit);
/* RDS is detected, as long as FM radio is selected assume
RDS will be available */
- extAttr->audData.rdsDataPresent = TRUE;
+ extAttr->audData.rdsDataPresent = true;
/* new data */
/* read the data */
RR16(addr, AUD_DEM_RD_RDS_ARRAY_CNT__A, &rRDSArrayCntCheck);
if (rRDSArrayCntCheck == rRDSArrayCntInit) {
- status->valid = TRUE;
+ status->valid = true;
extAttr->audData.rdsDataCounter = rRDSArrayCntCheck;
}
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
/* initialize the variables */
- status->carrierA = FALSE;
- status->carrierB = FALSE;
+ status->carrierA = false;
+ status->carrierB = false;
status->nicamStatus = DRX_AUD_NICAM_NOT_DETECTED;
- status->sap = FALSE;
- status->stereo = FALSE;
+ status->sap = false;
+ status->stereo = false;
/* read stereo sound mode indication */
RR16(devAddr, AUD_DEM_RD_STATUS__A, &rData);
/* carrier a detected */
if ((rData & AUD_DEM_RD_STATUS_STAT_CARR_A__M) ==
AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED) {
- status->carrierA = TRUE;
+ status->carrierA = true;
}
/* carrier b detected */
if ((rData & AUD_DEM_RD_STATUS_STAT_CARR_B__M) ==
AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED) {
- status->carrierB = TRUE;
+ status->carrierB = true;
}
/* nicam detected */
if ((rData & AUD_DEM_RD_STATUS_STAT_NICAM__M) ==
/* audio mode bilingual or SAP detected */
if ((rData & AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M) ==
AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP) {
- status->sap = TRUE;
+ status->sap = true;
}
/* stereo detected */
if ((rData & AUD_DEM_RD_STATUS_STAT_STEREO__M) ==
AUD_DEM_RD_STATUS_STAT_STEREO_STEREO) {
- status->stereo = TRUE;
+ status->stereo = true;
}
return DRX_STS_OK;
{
pDRXJData_t extAttr = NULL;
struct i2c_device_addr *devAddr = NULL;
- DRXCfgAudRDS_t rds = { FALSE, {0} };
+ DRXCfgAudRDS_t rds = { false, {0} };
u16 rData = 0;
if (status == NULL) {
CHK_ERROR(AUDCtrlGetCarrierDetectStatus(demod, status));
/* rds data */
- status->rds = FALSE;
+ status->rds = false;
CHK_ERROR(AUDCtrlGetCfgRDS(demod, &rds));
status->rds = extAttr->audData.rdsDataPresent;
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
/* volume */
volume->mute = extAttr->audData.volume.mute;
RR16(devAddr, AUD_DSP_WR_VOLUME__A, &rVolume);
if (rVolume == 0) {
- volume->mute = TRUE;
+ volume->mute = true;
volume->volume = extAttr->audData.volume.volume;
} else {
- volume->mute = FALSE;
+ volume->mute = false;
volume->volume = ((rVolume & AUD_DSP_WR_VOLUME_VOL_MAIN__M) >>
AUD_DSP_WR_VOLUME_VOL_MAIN__B) -
AUD_VOLUME_ZERO_DB;
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
/* volume */
/* clear the volume mask */
wVolume &= (u16) ~ AUD_DSP_WR_VOLUME_VOL_MAIN__M;
- if (volume->mute == TRUE) {
+ if (volume->mute == true) {
/* mute */
/* mute overrules volume */
wVolume |= (u16) (0);
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
RR16(devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig);
/* I2S output enabled */
if ((wI2SConfig & AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M)
== AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE) {
- output->outputEnable = TRUE;
+ output->outputEnable = true;
} else {
- output->outputEnable = FALSE;
+ output->outputEnable = false;
}
if (rI2SFreq > 0) {
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
RR16(devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig);
/* I2S output enabled */
wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M;
- if (output->outputEnable == TRUE) {
+ if (output->outputEnable == true) {
wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE;
} else {
wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE;
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
CHK_ERROR(AUDGetModus(demod, &rModus));
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
CHK_ERROR(AUDGetModus(demod, &rModus));
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
RR16(devAddr, AUD_DEM_RAM_A2_THRSHLD__A, &thresA2);
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
WR16(devAddr, AUD_DEM_WR_A2_THRSHLD__A, thres->a2);
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
CHK_ERROR(AUDGetModus(demod, &wModus));
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
CHK_ERROR(AUDGetModus(demod, &rModus));
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
/* Source Selctor */
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
/* Source Selctor */
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
/* audio/video synchronisation */
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
/* audio/video synchronisation */
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
/* read register data */
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
/* setting of max FM deviation */
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
if ((beep->volume > 0) || (beep->volume < -127)) {
}
theBeep |= (u16) frequency;
- if (beep->mute == TRUE) {
+ if (beep->mute == true) {
theBeep = 0;
}
u16 wModus = 0;
u16 rModus = 0;
- Bool_t muteBuffer = FALSE;
+ bool muteBuffer = false;
s16 volumeBuffer = 0;
u16 wVolume = 0;
extAttr = (pDRXJData_t) demod->myExtAttr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, FALSE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, false));
+ extAttr->audData.audioIsActive = true;
}
/* reset RDS data availability flag */
- extAttr->audData.rdsDataPresent = FALSE;
+ extAttr->audData.rdsDataPresent = false;
/* we need to mute from here to avoid noise during standard switching */
muteBuffer = extAttr->audData.volume.mute;
volumeBuffer = extAttr->audData.volume.volume;
- extAttr->audData.volume.mute = TRUE;
+ extAttr->audData.volume.mute = true;
/* restore data structure from DRX ExtAttr, call volume first to mute */
CHK_ERROR(AUDCtrlSetCfgVolume(demod, &extAttr->audData.volume));
CHK_ERROR(AUDCtrlSetCfgCarrier(demod, &extAttr->audData.carriers));
/* buffers intact */
/**************************************************************************/
extAttr->audData.volume.mute = muteBuffer;
- if (extAttr->audData.volume.mute == FALSE) {
+ if (extAttr->audData.volume.mute == false) {
wVolume |= (u16) ((volumeBuffer + AUD_VOLUME_ZERO_DB) <<
AUD_DSP_WR_VOLUME_VOL_MAIN__B);
WR16(devAddr, AUD_DSP_WR_VOLUME__A, wVolume);
devAddr = (struct i2c_device_addr *) demod->myI2CDevAddr;
/* power up */
- if (extAttr->audData.audioIsActive == FALSE) {
- CHK_ERROR(PowerUpAud(demod, TRUE));
- extAttr->audData.audioIsActive = TRUE;
+ if (extAttr->audData.audioIsActive == false) {
+ CHK_ERROR(PowerUpAud(demod, true));
+ extAttr->audData.audioIsActive = true;
}
*standard = DRX_AUD_STANDARD_UNKNOWN;
CHK_ERROR(AUDCtrlGetCarrierDetectStatus(demod, &status));
/* locked if either primary or secondary carrier is detected */
- if ((status.carrierA == TRUE) || (status.carrierB == TRUE)) {
+ if ((status.carrierA == true) || (status.carrierB == true)) {
*lockStat = DRX_LOCKED;
} else {
*lockStat = DRX_NOT_LOCKED;
s32 divisionFactor = 810;
u16 data = 0;
u32 symbolRate = 0;
- Bool_t negative = FALSE;
+ bool negative = false;
*SymbolRateOffset = 0;
/* read data rate */
unsignedTimingOffset = 32768;
else
unsignedTimingOffset = 0x00007FFF & (u32) (-data);
- negative = TRUE;
+ negative = true;
} else
unsignedTimingOffset = (u32) data;
*
*/
static DRXStatus_t
-GetOOBFreqOffset(pDRXDemodInstance_t demod, pDRXFrequency_t freqOffset)
+GetOOBFreqOffset(pDRXDemodInstance_t demod, s32 *freqOffset)
{
u16 data = 0;
u16 rot = 0;
*
*/
static DRXStatus_t
-GetOOBFrequency(pDRXDemodInstance_t demod, pDRXFrequency_t frequency)
+GetOOBFrequency(pDRXDemodInstance_t demod, s32 *frequency)
{
u16 data = 0;
- DRXFrequency_t freqOffset = 0;
- DRXFrequency_t freq = 0;
+ s32 freqOffset = 0;
+ s32 freq = 0;
struct i2c_device_addr *devAddr = NULL;
devAddr = demod->myI2CDevAddr;
SARR16(devAddr, SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A, &data);
- freq = (DRXFrequency_t) ((DRXFrequency_t) data * 50 + 50000L);
+ freq = (s32) ((s32) data * 50 + 50000L);
CHK_ERROR(GetOOBFreqOffset(demod, &freqOffset));
* \param active
* \return DRXStatus_t.
*/
-static DRXStatus_t SetOrxNsuAox(pDRXDemodInstance_t demod, Bool_t active)
+static DRXStatus_t SetOrxNsuAox(pDRXDemodInstance_t demod, bool active)
{
u16 data = 0;
struct i2c_device_addr *devAddr = NULL;
{
#ifndef DRXJ_DIGITAL_ONLY
DRXOOBDownstreamStandard_t standard = DRX_OOB_MODE_A;
- DRXFrequency_t freq = 0; /* KHz */
+ s32 freq = 0; /* KHz */
struct i2c_device_addr *devAddr = NULL;
pDRXJData_t extAttr = NULL;
u16 i = 0;
- Bool_t mirrorFreqSpectOOB = FALSE;
+ bool mirrorFreqSpectOOB = false;
u16 trkFilterValue = 0;
DRXJSCUCmd_t scuCmd;
u16 setParamParameters[3];
scuCmd.resultLen = 1;
scuCmd.result = cmdResult;
CHK_ERROR(SCUCommand(devAddr, &scuCmd));
- CHK_ERROR(SetOrxNsuAox(demod, FALSE));
+ CHK_ERROR(SetOrxNsuAox(demod, false));
WR16(devAddr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP);
- extAttr->oobPowerOn = FALSE;
+ extAttr->oobPowerOn = false;
return (DRX_STS_OK);
}
case DRX_OOB_MODE_A:
if (
/* signal is transmitted inverted */
- ((oobParam->spectrumInverted == TRUE) &
+ ((oobParam->spectrumInverted == true) &
/* and tuner is not mirroring the signal */
- (mirrorFreqSpectOOB == FALSE)) |
+ (mirrorFreqSpectOOB == false)) |
/* or */
/* signal is transmitted noninverted */
- ((oobParam->spectrumInverted == FALSE) &
+ ((oobParam->spectrumInverted == false) &
/* and tuner is mirroring the signal */
- (mirrorFreqSpectOOB == TRUE))
+ (mirrorFreqSpectOOB == true))
)
setParamParameters[0] =
SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC;
case DRX_OOB_MODE_B_GRADE_A:
if (
/* signal is transmitted inverted */
- ((oobParam->spectrumInverted == TRUE) &
+ ((oobParam->spectrumInverted == true) &
/* and tuner is not mirroring the signal */
- (mirrorFreqSpectOOB == FALSE)) |
+ (mirrorFreqSpectOOB == false)) |
/* or */
/* signal is transmitted noninverted */
- ((oobParam->spectrumInverted == FALSE) &
+ ((oobParam->spectrumInverted == false) &
/* and tuner is mirroring the signal */
- (mirrorFreqSpectOOB == TRUE))
+ (mirrorFreqSpectOOB == true))
)
setParamParameters[0] =
SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC;
default:
if (
/* signal is transmitted inverted */
- ((oobParam->spectrumInverted == TRUE) &
+ ((oobParam->spectrumInverted == true) &
/* and tuner is not mirroring the signal */
- (mirrorFreqSpectOOB == FALSE)) |
+ (mirrorFreqSpectOOB == false)) |
/* or */
/* signal is transmitted noninverted */
- ((oobParam->spectrumInverted == FALSE) &
+ ((oobParam->spectrumInverted == false) &
/* and tuner is mirroring the signal */
- (mirrorFreqSpectOOB == TRUE))
+ (mirrorFreqSpectOOB == true))
)
setParamParameters[0] =
SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC;
scuCmd.result = cmdResult;
CHK_ERROR(SCUCommand(devAddr, &scuCmd));
- CHK_ERROR(SetOrxNsuAox(demod, TRUE));
+ CHK_ERROR(SetOrxNsuAox(demod, true));
WR16(devAddr, ORX_NSU_AOX_STHR_W__A, extAttr->oobPreSaw);
- extAttr->oobPowerOn = TRUE;
+ extAttr->oobPowerOn = true;
return (DRX_STS_OK);
rw_error:
return (DRX_STS_INVALID_ARG);
}
- if (extAttr->oobPowerOn == FALSE)
+ if (extAttr->oobPowerOn == false)
return (DRX_STS_ERROR);
RR16(devAddr, ORX_DDC_OFO_SET_W__A, &data);
CtrlSetChannel(pDRXDemodInstance_t demod, pDRXChannel_t channel)
{
- DRXFrequency_t tunerSetFreq = 0;
- DRXFrequency_t tunerGetFreq = 0;
- DRXFrequency_t tunerFreqOffset = 0;
- DRXFrequency_t intermediateFreq = 0;
+ s32 tunerSetFreq = 0;
+ s32 tunerGetFreq = 0;
+ s32 tunerFreqOffset = 0;
+ s32 intermediateFreq = 0;
pDRXJData_t extAttr = NULL;
struct i2c_device_addr *devAddr = NULL;
DRXStandard_t standard = DRX_STANDARD_UNKNOWN;
TUNERMode_t tunerMode = 0;
pDRXCommonAttr_t commonAttr = NULL;
- Bool_t bridgeClosed = FALSE;
+ bool bridgeClosed = false;
#ifndef DRXJ_VSB_ONLY
u32 minSymbolRate = 0;
u32 maxSymbolRate = 0;
if ((extAttr->uioSmaTxMode) == DRX_UIO_MODE_FIRMWARE_SAW) {
/* SAW SW, user UIO is used for switchable SAW */
- DRXUIOData_t uio1 = { DRX_UIO1, FALSE };
+ DRXUIOData_t uio1 = { DRX_UIO1, false };
switch (channel->bandwidth) {
case DRX_BANDWIDTH_8MHZ:
- uio1.value = TRUE;
+ uio1.value = true;
break;
case DRX_BANDWIDTH_7MHZ:
- uio1.value = FALSE;
+ uio1.value = false;
break;
case DRX_BANDWIDTH_6MHZ:
- uio1.value = FALSE;
+ uio1.value = false;
break;
case DRX_BANDWIDTH_UNKNOWN:
default:
extAttr->frequency = tunerSetFreq;
if (commonAttr->tunerPortNr == 1) {
/* close tuner bridge */
- bridgeClosed = TRUE;
+ bridgeClosed = true;
CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed));
/* set tuner frequency */
}
tunerMode, tunerSetFreq));
if (commonAttr->tunerPortNr == 1) {
/* open tuner bridge */
- bridgeClosed = FALSE;
+ bridgeClosed = false;
CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed));
}
if (commonAttr->tunerPortNr == 1) {
/* close tuner bridge */
- bridgeClosed = TRUE;
+ bridgeClosed = true;
CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed));
}
tunerMode, tunerSetFreq));
if (commonAttr->tunerPortNr == 1) {
/* open tuner bridge */
- bridgeClosed = FALSE;
+ bridgeClosed = false;
CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed));
}
}
/* if ( demod->myTuner !=NULL ) */
/* flag the packet error counter reset */
- extAttr->resetPktErrAcc = TRUE;
+ extAttr->resetPktErrAcc = true;
return (DRX_STS_OK);
rw_error:
DRXLockStatus_t lockStatus = DRX_NOT_LOCKED;
DRXStandard_t standard = DRX_STANDARD_UNKNOWN;
pDRXCommonAttr_t commonAttr = NULL;
- DRXFrequency_t intermediateFreq = 0;
+ s32 intermediateFreq = 0;
s32 CTLFreqOffset = 0;
u32 iqmRcRateLo = 0;
u32 adcFrequency = 0;
channel->ldpc = DRX_LDPC_UNKNOWN;
if (demod->myTuner != NULL) {
- DRXFrequency_t tunerFreqOffset = 0;
- Bool_t tunerMirror = commonAttr->mirrorFreqSpect ? FALSE : TRUE;
+ s32 tunerFreqOffset = 0;
+ bool tunerMirror = commonAttr->mirrorFreqSpect ? false : true;
/* Get frequency from tuner */
CHK_ERROR(DRXBSP_TUNER_GetFrequency(demod->myTuner,
&(channel->frequency),
&intermediateFreq));
tunerFreqOffset = channel->frequency - extAttr->frequency;
- if (tunerMirror == TRUE) {
+ if (tunerMirror == true) {
/* positive image */
channel->frequency += tunerFreqOffset;
} else {
case DRX_STANDARD_ITU_A: /* fallthrough */
case DRX_STANDARD_ITU_B: /* fallthrough */
case DRX_STANDARD_ITU_C:
- CHK_ERROR(PowerDownQAM(demod, FALSE));
+ CHK_ERROR(PowerDownQAM(demod, false));
break;
#endif
case DRX_STANDARD_8VSB:
- CHK_ERROR(PowerDownVSB(demod, FALSE));
+ CHK_ERROR(PowerDownVSB(demod, false));
break;
#ifndef DRXJ_DIGITAL_ONLY
case DRX_STANDARD_NTSC: /* fallthrough */
case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */
case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */
case DRX_STANDARD_PAL_SECAM_LP:
- CHK_ERROR(PowerDownATV(demod, prevStandard, FALSE));
+ CHK_ERROR(PowerDownATV(demod, prevStandard, false));
break;
#endif
case DRX_STANDARD_UNKNOWN:
case DRX_STANDARD_ITU_A:
case DRX_STANDARD_ITU_B:
case DRX_STANDARD_ITU_C:
- CHK_ERROR(PowerDownQAM(demod, TRUE));
+ CHK_ERROR(PowerDownQAM(demod, true));
break;
case DRX_STANDARD_8VSB:
- CHK_ERROR(PowerDownVSB(demod, TRUE));
+ CHK_ERROR(PowerDownVSB(demod, true));
break;
case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */
case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */
case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */
case DRX_STANDARD_NTSC: /* fallthrough */
case DRX_STANDARD_FM:
- CHK_ERROR(PowerDownATV(demod, extAttr->standard, TRUE));
+ CHK_ERROR(PowerDownATV(demod, extAttr->standard, true));
break;
case DRX_STANDARD_UNKNOWN:
/* Do nothing */
extAttr->vVersion[0].moduleName = ucodeName;
extAttr->vVersion[0].vString = extAttr->vText[0];
- if (commonAttr->isOpened == TRUE) {
+ if (commonAttr->isOpened == true) {
SARR16(devAddr, SCU_RAM_VERSION_HI__A, &ucodeMajorMinor);
SARR16(devAddr, SCU_RAM_VERSION_LO__A, &ucodePatch);
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
- if (commonAttr->isOpened == FALSE
+ if (commonAttr->isOpened == false
|| commonAttr->currentPowerMode != DRX_POWER_UP) {
struct i2c_device_addr *devAddr = NULL;
DRXPowerMode_t powerMode = DRX_POWER_UP;
/* Remeber original power mode */
orgPowerMode = commonAttr->currentPowerMode;
- if (demod->myCommonAttr->isOpened == FALSE) {
+ if (demod->myCommonAttr->isOpened == false) {
CHK_ERROR(PowerUpDevice(demod));
commonAttr->currentPowerMode = DRX_POWER_UP;
} else {
* \fn DRXStatus_t IsMCBlockAudio()
* \brief Check if MC block is Audio or not Audio.
* \param addr Pointer to demodulator instance.
-* \param audioUpload TRUE if MC block is Audio
- FALSE if MC block not Audio
-* \return Bool_t.
+* \param audioUpload true if MC block is Audio
+ false if MC block not Audio
+* \return bool.
*/
-Bool_t IsMCBlockAudio(u32 addr)
+bool IsMCBlockAudio(u32 addr)
{
if ((addr == AUD_XFP_PRAM_4K__A) || (addr == AUD_XDFP_PRAM_4K__A)) {
- return (TRUE);
+ return (true);
}
- return (FALSE);
+ return (false);
}
/*============================================================================*/
* \param demod Pointer to demodulator instance.
* \param mcInfo Pointer to information about microcode data.
* \param action Either UCODE_UPLOAD or UCODE_VERIFY.
-* \param uploadAudioMC TRUE if Audio MC need to be uploaded.
- FALSE if !Audio MC need to be uploaded.
+* \param uploadAudioMC true if Audio MC need to be uploaded.
+ false if !Audio MC need to be uploaded.
* \return DRXStatus_t.
*/
static DRXStatus_t
CtrlUCodeUpload(pDRXDemodInstance_t demod,
pDRXUCodeInfo_t mcInfo,
- DRXUCodeAction_t action, Bool_t uploadAudioMC)
+ DRXUCodeAction_t action, bool uploadAudioMC)
{
u16 i = 0;
u16 mcNrOfBlks = 0;
mcData += mcBlockNrBytes;
} /* for( i = 0 ; i<mcNrOfBlks ; i++ ) */
- if (uploadAudioMC == FALSE) {
- extAttr->flagAudMcUploaded = FALSE;
+ if (uploadAudioMC == false) {
+ extAttr->flagAudMcUploaded = false;
}
return (DRX_STS_OK);
SARR16(devAddr, SCU_RAM_ORX_SCU_LOCK__A, &lock);
- misc->anaGainLock = ((lock & 0x0001) ? TRUE : FALSE);
- misc->digGainLock = ((lock & 0x0002) ? TRUE : FALSE);
- misc->freqLock = ((lock & 0x0004) ? TRUE : FALSE);
- misc->phaseLock = ((lock & 0x0008) ? TRUE : FALSE);
- misc->symTimingLock = ((lock & 0x0010) ? TRUE : FALSE);
- misc->eqLock = ((lock & 0x0020) ? TRUE : FALSE);
+ misc->anaGainLock = ((lock & 0x0001) ? true : false);
+ misc->digGainLock = ((lock & 0x0002) ? true : false);
+ misc->freqLock = ((lock & 0x0004) ? true : false);
+ misc->phaseLock = ((lock & 0x0008) ? true : false);
+ misc->symTimingLock = ((lock & 0x0010) ? true : false);
+ misc->eqLock = ((lock & 0x0020) ? true : false);
SARR16(devAddr, SCU_RAM_ORX_SCU_STATE__A, &state);
misc->state = (state >> 8) & 0xff;
case DRX_STANDARD_NTSC: /* fallthrough */
case DRX_STANDARD_FM:
#endif
- return SetAgcIf(demod, agcSettings, TRUE);
+ return SetAgcIf(demod, agcSettings, true);
case DRX_STANDARD_UNKNOWN:
default:
return (DRX_STS_INVALID_ARG);
case DRX_STANDARD_NTSC: /* fallthrough */
case DRX_STANDARD_FM:
#endif
- return SetAgcRf(demod, agcSettings, TRUE);
+ return SetAgcRf(demod, agcSettings, true);
case DRX_STANDARD_UNKNOWN:
default:
return (DRX_STS_INVALID_ARG);
(pDRXCfgMPEGOutput_t) config->
cfgData);
case DRX_CFG_PINS_SAFE_MODE:
- return CtrlSetCfgPdrSafeMode(demod, (pBool_t) config->cfgData);
+ return CtrlSetCfgPdrSafeMode(demod, (bool *) config->cfgData);
case DRXJ_CFG_AGC_RF:
return CtrlSetCfgAgcRf(demod, (pDRXJCfgAgc_t) config->cfgData);
case DRXJ_CFG_AGC_IF:
(pDRXCfgMPEGOutput_t) config->
cfgData);
case DRX_CFG_PINS_SAFE_MODE:
- return CtrlGetCfgPdrSafeMode(demod, (pBool_t) config->cfgData);
+ return CtrlGetCfgPdrSafeMode(demod, (bool *) config->cfgData);
case DRXJ_CFG_AGC_RF:
return CtrlGetCfgAgcRf(demod, (pDRXJCfgAgc_t) config->cfgData);
case DRXJ_CFG_AGC_IF:
WR16(devAddr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)
| ATV_TOP_STDBY_SIF_STDBY_STANDBY);
- CHK_ERROR(SetIqmAf(demod, FALSE));
- CHK_ERROR(SetOrxNsuAox(demod, FALSE));
+ CHK_ERROR(SetIqmAf(demod, false));
+ CHK_ERROR(SetOrxNsuAox(demod, false));
CHK_ERROR(InitHI(demod));
/* disable mpegoutput pins */
- cfgMPEGOutput.enableMPEGOutput = FALSE;
+ cfgMPEGOutput.enableMPEGOutput = false;
CHK_ERROR(CtrlSetCfgMPEGOutput(demod, &cfgMPEGOutput));
/* Stop AUD Inform SetAudio it will need to do all setting */
CHK_ERROR(PowerDownAud(demod));
if (commonAttr->microcode != NULL) {
/* Dirty trick to use common ucode upload & verify,
pretend device is already open */
- commonAttr->isOpened = TRUE;
+ commonAttr->isOpened = true;
ucodeInfo.mcData = commonAttr->microcode;
ucodeInfo.mcSize = commonAttr->microcodeSize;
#ifdef DRXJ_SPLIT_UCODE_UPLOAD
/* Upload microcode without audio part */
CHK_ERROR(CtrlUCodeUpload
- (demod, &ucodeInfo, UCODE_UPLOAD, FALSE));
+ (demod, &ucodeInfo, UCODE_UPLOAD, false));
#else
CHK_ERROR(DRX_Ctrl(demod, DRX_CTRL_LOAD_UCODE, &ucodeInfo));
#endif /* DRXJ_SPLIT_UCODE_UPLOAD */
- if (commonAttr->verifyMicrocode == TRUE) {
+ if (commonAttr->verifyMicrocode == true) {
#ifdef DRXJ_SPLIT_UCODE_UPLOAD
CHK_ERROR(CtrlUCodeUpload
- (demod, &ucodeInfo, UCODE_VERIFY, FALSE));
+ (demod, &ucodeInfo, UCODE_VERIFY, false));
#else
CHK_ERROR(DRX_Ctrl
(demod, DRX_CTRL_VERIFY_UCODE, &ucodeInfo));
#endif /* DRXJ_SPLIT_UCODE_UPLOAD */
}
- commonAttr->isOpened = FALSE;
+ commonAttr->isOpened = false;
}
/* Run SCU for a little while to initialize microcode version numbers */
demod->myTuner->myCommonAttr->myUserData = (void *)demod;
if (commonAttr->tunerPortNr == 1) {
- Bool_t bridgeClosed = TRUE;
+ bool bridgeClosed = true;
CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed));
}
CHK_ERROR(DRXBSP_TUNER_Open(demod->myTuner));
if (commonAttr->tunerPortNr == 1) {
- Bool_t bridgeClosed = FALSE;
+ bool bridgeClosed = false;
CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed));
}
commonAttr->tunerMinFreqRF =
extAttr->qamRfAgcCfg.cutOffCurrent = 4000;
extAttr->qamPreSawCfg.standard = DRX_STANDARD_ITU_B;
extAttr->qamPreSawCfg.reference = 0x07;
- extAttr->qamPreSawCfg.usePreSaw = TRUE;
+ extAttr->qamPreSawCfg.usePreSaw = true;
#endif
/* Initialize default AFE configuartion for VSB */
extAttr->vsbRfAgcCfg.standard = DRX_STANDARD_8VSB;
extAttr->vsbRfAgcCfg.cutOffCurrent = 4000;
extAttr->vsbPreSawCfg.standard = DRX_STANDARD_8VSB;
extAttr->vsbPreSawCfg.reference = 0x07;
- extAttr->vsbPreSawCfg.usePreSaw = TRUE;
+ extAttr->vsbPreSawCfg.usePreSaw = true;
#ifndef DRXJ_DIGITAL_ONLY
/* Initialize default AFE configuartion for ATV */
extAttr->atvIfAgcCfg.speed = 3;
extAttr->atvIfAgcCfg.top = 2400;
extAttr->atvPreSawCfg.reference = 0x0007;
- extAttr->atvPreSawCfg.usePreSaw = TRUE;
+ extAttr->atvPreSawCfg.usePreSaw = true;
extAttr->atvPreSawCfg.standard = DRX_STANDARD_NTSC;
#endif
extAttr->standard = DRX_STANDARD_UNKNOWN;
return (DRX_STS_OK);
rw_error:
- commonAttr->isOpened = FALSE;
+ commonAttr->isOpened = false;
return (DRX_STS_ERROR);
}
if (demod->myTuner != NULL) {
/* Check if bridge is used */
if (commonAttr->tunerPortNr == 1) {
- Bool_t bridgeClosed = TRUE;
+ bool bridgeClosed = true;
CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed));
}
CHK_ERROR(DRXBSP_TUNER_Close(demod->myTuner));
if (commonAttr->tunerPortNr == 1) {
- Bool_t bridgeClosed = FALSE;
+ bool bridgeClosed = false;
CHK_ERROR(CtrlI2CBridge(demod, &bridgeClosed));
}
};
/*======================================================================*/
case DRX_CTRL_I2C_BRIDGE:
{
- return CtrlI2CBridge(demod, (pBool_t) ctrlData);
+ return CtrlI2CBridge(demod, (bool *) ctrlData);
}
break;
/*======================================================================*/
{
return CtrlUCodeUpload(demod,
(pDRXUCodeInfo_t) ctrlData,
- UCODE_UPLOAD, FALSE);
+ UCODE_UPLOAD, false);
}
break;
case DRX_CTRL_VERIFY_UCODE:
{
return CtrlUCodeUpload(demod,
(pDRXUCodeInfo_t) ctrlData,
- UCODE_VERIFY, FALSE);
+ UCODE_VERIFY, false);
}
break;
#endif /* DRXJ_SPLIT_UCODE_UPLOAD */
projects / openwrt / staging / blogic.git / commitdiff