CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_ARCH_ASPEED is not set
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_CNS3XXX=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_NR_GPIO=0
-# CONFIG_ARCH_OMAP2 is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-# CONFIG_ARCH_WM8750 is not set
CONFIG_ARM=y
# CONFIG_ARM_CPU_SUSPEND is not set
CONFIG_ARM_GIC=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EEPROM_AT24=y
-# CONFIG_EFI is not set
CONFIG_FIQ=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_GLOB=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
-# CONFIG_GPIO_MPC8XXX is not set
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GPIO_SYSFS=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_UID16=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-# CONFIG_HISI_FEMAC is not set
CONFIG_HWMON=y
CONFIG_HZ_FIXED=0
CONFIG_HZ_PERIODIC=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
-CONFIG_LCD_DOGM132=y
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_TRIGGER_MTD is not set
# CONFIG_LEDS_TRIGGER_NETDEV is not set
# CONFIG_MACH_CNS3420VB is not set
CONFIG_MACH_GW2388=y
CONFIG_MDIO_BOARDINFO=y
-# CONFIG_MDIO_HISI_FEMAC is not set
-# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_MAX77620 is not set
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGHT_HAVE_PCI=y
CONFIG_MMC_SDHCI_PLTFM=y
# CONFIG_MMC_TIFM_SD is not set
CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MPCORE_WATCHDOG=y
CONFIG_MTD_M25P80=y
# CONFIG_MTD_OF_PARTS is not set
CONFIG_MTD_PHYSMAP=y
CONFIG_PL310_ERRATA_769419=y
CONFIG_PPS=y
CONFIG_PPS_CLIENT_GPIO=y
-CONFIG_PWRSEQ_EMMC=y
-CONFIG_PWRSEQ_SIMPLE=y
CONFIG_RAID_ATTRS=y
CONFIG_RATIONAL=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_USE_OF=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_VFP=y
+CONFIG_WATCHDOG_CORE=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_XPS=y
CONFIG_XZ_DEC_ARM=y
-1. Made the connection between CNS3xxx SOCs(ARCH_CNS3xxx) and MPcore watchdog
- since the CNS3xxx SOCs have ARM11 MPcore CPU.
-2. Enable mpcore_watchdog option as module to default configuration at
- arch/arm/configs/cns3420vb_defconfig.
-
-Signed-off-by: Tommy Lin <tommy.lin@caviumnetworks.com>
+Add a watchdog driver for ARM MPcore processors.
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
-arch/arm/Kconfig | 1 +
- arch/arm/configs/cns3420vb_defconfig | 2 ++
- arch/arm/mach-cns3xxx/cns3420vb.c | 22 ++++++++++++++++++++++
- 3 files changed, 25 insertions(+), 0 deletions(-)
-
---- a/arch/arm/configs/cns3420vb_defconfig
-+++ b/arch/arm/configs/cns3420vb_defconfig
-@@ -56,6 +56,8 @@ CONFIG_LEGACY_PTY_COUNT=16
- # CONFIG_HW_RANDOM is not set
- # CONFIG_HWMON is not set
- # CONFIG_VGA_CONSOLE is not set
-+CONFIG_WATCHDOG=y
-+CONFIG_MPCORE_WATCHDOG=m
- # CONFIG_HID_SUPPORT is not set
- # CONFIG_USB_SUPPORT is not set
- CONFIG_MMC=y
---- a/arch/arm/mach-cns3xxx/cns3420vb.c
-+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
-@@ -206,10 +206,32 @@ static struct platform_device cns3xxx_us
- },
- };
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -324,6 +324,13 @@ config KS8695_WATCHDOG
+ Watchdog timer embedded into KS8695 processor. This will reboot your
+ system when the timeout is reached.
-+/* Watchdog */
-+static struct resource cns3xxx_watchdog_resources[] = {
-+ [0] = {
-+ .start = CNS3XXX_TC11MP_TWD_BASE,
-+ .end = CNS3XXX_TC11MP_TWD_BASE + PAGE_SIZE - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = IRQ_LOCALWDOG,
-+ .end = IRQ_LOCALWDOG,
-+ .flags = IORESOURCE_IRQ,
-+ }
++config MPCORE_WATCHDOG
++ tristate "MPcore watchdog"
++ depends on HAVE_ARM_TWD
++ select WATCHDOG_CORE
++ help
++ Watchdog timer embedded into the MPcore system
++
+ config HAVE_S3C2410_WATCHDOG
+ bool
+ help
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -47,6 +47,7 @@ obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
+ obj-$(CONFIG_977_WATCHDOG) += wdt977.o
+ obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
+ obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o
++obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o
+ obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o
+ obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o
+ obj-$(CONFIG_SAMA5D4_WATCHDOG) += sama5d4_wdt.o
+--- /dev/null
++++ b/drivers/watchdog/mpcore_wdt.c
+@@ -0,0 +1,117 @@
++/*
++ * Watchdog driver for ARM MPcore
++ *
++ * Copyright (C) 2017 Felix Fietkau <nbd@nbd.name>
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/watchdog.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <asm/smp_twd.h>
++
++static void __iomem *wdt_base;
++static int wdt_timeout = 60;
++
++static int mpcore_wdt_keepalive(struct watchdog_device *wdd)
++{
++ static int perturb;
++ u32 count;
++
++ count = ioread32(wdt_base + TWD_WDOG_COUNTER);
++ count = (~0U - count) * HZ / 5;
++ count /= 256; /* prescale */
++ count *= wdt_timeout;
++
++ /* Reload register needs a different value on each refresh */
++ count += perturb;
++ perturb = !perturb;
++
++ iowrite32(count, wdt_base + TWD_WDOG_LOAD);
++
++ return 0;
++}
++
++static int mpcore_wdt_start(struct watchdog_device *wdd)
++{
++ mpcore_wdt_keepalive(wdd);
++
++ /* prescale = 256, mode = 1, enable = 1 */
++ iowrite32(0x0000FF09, wdt_base + TWD_WDOG_CONTROL);
++
++ return 0;
++}
++
++static int mpcore_wdt_stop(struct watchdog_device *wdd)
++{
++ iowrite32(0x12345678, wdt_base + TWD_WDOG_DISABLE);
++ iowrite32(0x87654321, wdt_base + TWD_WDOG_DISABLE);
++ iowrite32(0x0, wdt_base + TWD_WDOG_CONTROL);
++
++ return 0;
++}
++
++static int mpcore_wdt_set_timeout(struct watchdog_device *wdd,
++ unsigned int timeout)
++{
++ mpcore_wdt_stop(wdd);
++ wdt_timeout = timeout;
++ mpcore_wdt_start(wdd);
++
++ return 0;
++}
++
++static const struct watchdog_info mpcore_wdt_info = {
++ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
++ .identity = "MPcore Watchdog",
++};
++
++static const struct watchdog_ops mpcore_wdt_ops = {
++ .owner = THIS_MODULE,
++ .start = mpcore_wdt_start,
++ .stop = mpcore_wdt_stop,
++ .ping = mpcore_wdt_keepalive,
++ .set_timeout = mpcore_wdt_set_timeout,
++};
++
++static struct watchdog_device mpcore_wdt = {
++ .info = &mpcore_wdt_info,
++ .ops = &mpcore_wdt_ops,
++ .min_timeout = 1,
++ .max_timeout = 65535,
+};
+
-+static struct platform_device cns3xxx_watchdog_device = {
-+ .name = "mpcore_wdt",
-+ .id = -1,
-+ .num_resources = ARRAY_SIZE(cns3xxx_watchdog_resources),
-+ .resource = cns3xxx_watchdog_resources,
++static int mpcore_wdt_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENODEV;
++
++ wdt_base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(wdt_base))
++ return PTR_ERR(wdt_base);
++
++ watchdog_register_device(&mpcore_wdt);
++ return 0;
++}
++
++static int mpcore_wdt_remove(struct platform_device *dev)
++{
++ watchdog_unregister_device(&mpcore_wdt);
++ return 0;
++}
++
++static struct platform_driver mpcore_wdt_driver = {
++ .probe = mpcore_wdt_probe,
++ .remove = mpcore_wdt_remove,
++ .driver = {
++ .name = "mpcore_wdt",
++ },
+};
+
- /*
- * Initialization
- */
- static struct platform_device *cns3420_pdevs[] __initdata = {
-+ &cns3xxx_watchdog_device,
- &cns3420_nor_pdev,
- &cns3xxx_usb_ehci_device,
- &cns3xxx_usb_ohci_device,
++module_platform_driver(mpcore_wdt_driver);
++MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
++MODULE_LICENSE("GPL");
projects / openwrt / staging / thess.git / commitdiff