powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040
authorAneesh Bansal <aneesh.bansal@freescale.com>
Tue, 16 Jun 2015 05:06:30 +0000 (10:36 +0530)
committerYork Sun <yorksun@freescale.com>
Fri, 31 Jul 2015 15:50:18 +0000 (08:50 -0700)
Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.

The targets for P5020 and P5040 are added in the same manner.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
board/freescale/corenet_ds/MAINTAINERS
configs/P5020DS_NAND_SECURE_BOOT_defconfig [new file with mode: 0644]
configs/P5040DS_NAND_SECURE_BOOT_defconfig [new file with mode: 0644]

index 6855446ca82a03bbb77be9d3d57ef28a6cfac9fe..73b0553184e78a352f90ae00155aa995d96f3604 100644 (file)
@@ -33,3 +33,5 @@ CORENET_DS_SECURE_BOOT BOARD
 M:     Aneesh Bansal <aneesh.bansal@freescale.com>
 S:     Maintained
 F:     configs/P3041DS_NAND_SECURE_BOOT_defconfig
+F:     configs/P5020DS_NAND_SECURE_BOOT_defconfig
+F:     configs/P5040DS_NAND_SECURE_BOOT_defconfig
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
new file mode 100644 (file)
index 0000000..98cdd35
--- /dev/null
@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P5020DS=y
+CONFIG_SPI_FLASH=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
new file mode 100644 (file)
index 0000000..a6cc7c4
--- /dev/null
@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P5040DS=y
+CONFIG_SPI_FLASH=y