drm/i915: Update DSPCNTR gamma/csc bits during crtc_enable()

On g4x+ we depend on the primary plane DSPCNTR gamma/csc enable
bits for the pipe bottom color. To guarantee that those are
correct already when enabling the crtc let's do an explicit
->disable_plane() call before enabling the pipe.

On skl+ this will be handled by the explicit PIPE_BOTTOM_COLOR
register which is already part of the normal color commit we
do durign crtc enable.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190207202146.26423-8-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 09888cc2c134dfc7b912bfe13c63ec79262c531b..c0e2806febf6116647f0cac44098663ceb982f83 100644 (file)
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -663,6 +663,10 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
                intel_atomic_get_old_crtc_state(state, crtc);
        struct intel_plane *plane;
 
+       if (!new_crtc_state->base.active ||
+           drm_atomic_crtc_needs_modeset(&new_crtc_state->base))
+               return 0;
+
        if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
            new_crtc_state->csc_enable == old_crtc_state->csc_enable)
                return 0;

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 78f46a94733d57bdd442f4683915b6a5cce77744..c496b6e0226b025f1ea99bec3523c620dc9edb6c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5742,6 +5742,14 @@ static void intel_encoders_update_pipe(struct drm_crtc *crtc,
        }
 }
 
+static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
+{
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+       struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+
+       plane->disable_plane(plane, crtc_state);
+}
+
 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
                                 struct drm_atomic_state *old_state)
 {
@@ -5807,6 +5815,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
         */
        intel_color_load_luts(pipe_config);
        intel_color_commit(pipe_config);
+       /* update DSPCNTR to configure gamma for pipe bottom color */
+       intel_disable_primary_plane(pipe_config);
 
        if (dev_priv->display.initial_watermarks != NULL)
                dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
@@ -5935,6 +5945,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
         */
        intel_color_load_luts(pipe_config);
        intel_color_commit(pipe_config);
+       /* update DSPCNTR to configure gamma/csc for pipe bottom color */
+       if (INTEL_GEN(dev_priv) < 9)
+               intel_disable_primary_plane(pipe_config);
 
        if (INTEL_GEN(dev_priv) >= 11)
                icl_set_pipe_chicken(intel_crtc);
@@ -6292,6 +6305,8 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
 
        intel_color_load_luts(pipe_config);
        intel_color_commit(pipe_config);
+       /* update DSPCNTR to configure gamma for pipe bottom color */
+       intel_disable_primary_plane(pipe_config);
 
        dev_priv->display.initial_watermarks(old_intel_state,
                                             pipe_config);
@@ -6349,6 +6364,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
 
        intel_color_load_luts(pipe_config);
        intel_color_commit(pipe_config);
+       /* update DSPCNTR to configure gamma for pipe bottom color */
+       intel_disable_primary_plane(pipe_config);
 
        if (dev_priv->display.initial_watermarks != NULL)
                dev_priv->display.initial_watermarks(old_intel_state,