drm/amd/display: Fix Maximus pixel clock programming

Maximus testing now defaults to a 700 MHz emulated dispclk

Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 31280d2527534552eccde034369293086f416cf9..5036b674f68b3ff37badfbdd303448359b5c9740 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -908,19 +908,9 @@ static bool dce110_program_pix_clk(
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
        if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
                unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
-               unsigned dp_dto_ref_kHz = 600000;
-               /* DPREF clock from FPGA TODO: Does FPGA have this value? */
+               unsigned dp_dto_ref_kHz = 700000;
                unsigned clock_kHz = pll_settings->actual_pix_clk;
 
-               /* For faster simulation, if mode pixe clock less than 290MHz,
-                * pixel clock can be hard coded to 290Mhz. For 4K mode, pixel clock
-                * is greater than 500Mhz, need real pixel clock
-                * clock_kHz = 290000;
-                */
-               /* TODO: un-hardcode when we can set display clock properly*/
-               /*clock_kHz = pix_clk_params->requested_pix_clk;*/
-               clock_kHz = 290000;
-
                /* Set DTO values: phase = target clock, modulo = reference clock */
                REG_WRITE(PHASE[inst], clock_kHz);
                REG_WRITE(MODULO[inst], dp_dto_ref_kHz);