clk: qcom: msm8960: fix ce3_core clk enable register

This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index 983dd7dc89a7970e3c1c8d35a427a56b48959929..63ecd97f379327a2db6f973e4500e0e2d7b38f72 100644 (file)
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -2769,7 +2769,7 @@ static struct clk_branch ce3_core_clk = {
        .halt_reg = 0x2fdc,
        .halt_bit = 5,
        .clkr = {
-               .enable_reg = 0x36c4,
+               .enable_reg = 0x36cc,
                .enable_mask = BIT(4),
                .hw.init = &(struct clk_init_data){
                        .name = "ce3_core_clk",