pinctrl-0 = <&state_default>;
state_default: pinmux {
- nand_out {
- lantiq,groups = "nand cle", "nand ale";
- lantiq,function = "ebu";
- lantiq,output = <1>;
- lantiq,open-drain = <0>;
- lantiq,pull = <0>;
- };
- nand_cs1 {
- lantiq,groups = "nand cs1";
- lantiq,function = "ebu";
- lantiq,open-drain = <0>;
- lantiq,pull = <0>;
- };
exin {
lantiq,groups = "exin1";
lantiq,function = "exin";
reg = <1 0x0 0x2000000 >;
req-mask = <0x1>; /* PCI request lines to mask during NAND access */
+ pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
+ pinctrl-names = "default";
+
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
pinctrl-0 = <&state_default>;
state_default: pinmux {
- nand_out {
- lantiq,groups = "nand cle", "nand ale";
- lantiq,function = "ebu";
- lantiq,output = <1>;
- lantiq,open-drain = <0>;
- lantiq,pull = <0>;
- };
- nand_cs1 {
- lantiq,groups = "nand cs1";
- lantiq,function = "ebu";
- lantiq,open-drain = <0>;
- lantiq,pull = <0>;
- };
-
pci_in {
lantiq,groups = "req1";
lantiq,function = "pci";
reg = <1 0x0 0x2000000 >;
req-mask = <0x1>; /* PCI request lines to mask during NAND access */
+ pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
+ pinctrl-names = "default";
+
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
lantiq,open-drain = <0>;
lantiq,output = <1>;
};
- nand_out {
- lantiq,groups = "nand cle", "nand ale";
- lantiq,function = "ebu";
- lantiq,output = <1>;
- lantiq,open-drain = <0>;
- lantiq,pull = <0>;
- };
- nand_cs1 {
- lantiq,groups = "nand cs1";
- lantiq,function = "ebu";
- lantiq,open-drain = <0>;
- lantiq,pull = <0>;
- };
};
};
lantiq,cs = <1>;
bank-width = <2>;
reg = <0x1 0x0 0x2000000>;
+
+ pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
+ pinctrl-names = "default";
+
nand-on-flash-bbt;
nand-ecc-strength = <3>;
nand-ecc-step-size = <256>;
lantiq,groups = "stp";
lantiq,function = "stp";
};
- nand {
- lantiq,groups = "nand cle", "nand ale",
- "nand rd", "nand rdy";
- lantiq,function = "ebu";
- };
pci {
lantiq,groups = "gnt1", "req1";
lantiq,function = "pci";
};
conf_out {
- lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
- "io4", "io5", "io6", /* stp */
+ lantiq,pins = "io4", "io5", "io6", /* stp */
"io21",
"io33";
lantiq,open-drain;
lantiq,output = <1>;
};
conf_in {
- lantiq,pins = "io39", /* exin3 */
- "io48"; /* nand rdy */
+ lantiq,pins = "io39"; /* exin3 */
lantiq,pull = <2>;
};
};
bank-width = <2>;
reg = <0 0x0 0x2000000>;
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
bank-width = <2>;
reg = <1 0x0 0x2000000>;
+ pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
+ pinctrl-names = "default";
+
nand-ecc-mode = "soft";
nand-ecc-strength = <3>;
nand-ecc-step-size = <256>;
bank-width = <2>;
reg = <1 0x0 0x2000000>;
+ pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
+ pinctrl-names = "default";
+
nand-ecc-mode = "on-die";
partitions {
pinctrl-0 = <&state_default>;
state_default: pinmux {
- nand {
- lantiq,groups = "nand cle", "nand ale",
- "nand rd", "nand cs1", "nand rdy";
- lantiq,function = "ebu";
- lantiq,pull = <1>;
- };
-
phy-rst {
lantiq,pins = "io37", "io44";
lantiq,pull = <0>;
};
&state_default {
- nand {
- lantiq,groups = "nand ale", "nand cle",
- "nand cs1", "nand rd", "nand rdy";
- lantiq,function = "ebu";
- };
-
pcie-rst {
lantiq,pins = "io21";
lantiq,open-drain = <1>;
lantiq,cs1 = <1>;
bank-width = <1>;
reg = <1 0x0 0x2000000>;
+
+ pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
+ pinctrl-names = "default";
+
nand-ecc-mode = "on-die";
partitions {
reg = <0 0x0 0x2000000>;
lantiq,cs = <1>;
+ pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
+ pinctrl-names = "default";
+
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
lantiq,open-drain = <1>;
lantiq,output = <1>;
};
- nand-mux {
- lantiq,groups = "nand cle", "nand ale",
- "nand rd", "nand cs1",
- "nand rdy";
- lantiq,function = "ebu";
- };
- nand-pins {
- lantiq,pins = "io13", "io24", "io49";
- lantiq,pull = <1>;
- };
};
};
bank-width = <2>;
reg = <0 0x0 0x2000000>;
+ pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
+ pinctrl-names = "default";
+
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
bank-width = <2>;
reg = <0 0x0 0x800000>;
+ pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
+ pinctrl-names = "default";
+
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
lantiq,open-drain = <0>;
lantiq,output = <1>;
};
- nand_out {
- lantiq,groups = "nand cle", "nand ale";
- lantiq,function = "ebu";
- lantiq,output = <1>;
- lantiq,open-drain = <0>;
- lantiq,pull = <0>;
- };
- nand_cs1 {
- lantiq,groups = "nand cs1";
- lantiq,function = "ebu";
- lantiq,open-drain = <0>;
- lantiq,pull = <0>;
- };
};
};
};
};
+ nand_pins: nand {
+ mux-0 {
+ lantiq,groups = "nand cle", "nand ale",
+ "nand rd";
+ lantiq,function = "ebu";
+ lantiq,output = <1>;
+ lantiq,open-drain = <0>;
+ lantiq,pull = <0>;
+ };
+ mux-1 {
+ lantiq,groups = "nand rdy";
+ lantiq,function = "ebu";
+ lantiq,output = <0>;
+ lantiq,pull = <2>;
+ };
+ };
+
+ nand_cs1_pins: nand-cs1 {
+ mux {
+ lantiq,groups = "nand cs1";
+ lantiq,function = "ebu";
+ lantiq,open-drain = <0>;
+ lantiq,pull = <0>;
+ };
+ };
+
spi_pins: spi {
mux-0 {
lantiq,groups = "spi_di";
#gpio-cells = <2>;
gpio-controller;
reg = <0xe100b10 0xa0>;
+
+ nand_pins: nand {
+ mux-0 {
+ lantiq,groups = "nand cle", "nand ale",
+ "nand rd";
+ lantiq,function = "ebu";
+ lantiq,output = <1>;
+ lantiq,open-drain = <0>;
+ lantiq,pull = <0>;
+ };
+ mux-1 {
+ lantiq,groups = "nand rdy";
+ lantiq,function = "ebu";
+ lantiq,output = <0>;
+ lantiq,pull = <2>;
+ };
+ };
+
+ nand_cs1_pins: nand-cs1 {
+ mux {
+ lantiq,groups = "nand cs1";
+ lantiq,function = "ebu";
+ lantiq,open-drain = <0>;
+ lantiq,pull = <0>;
+ };
+ };
};
asc1: serial@e100c00 {
};
};
+ nand_pins: nand {
+ mux-0 {
+ lantiq,groups = "nand cle", "nand ale",
+ "nand rd";
+ lantiq,function = "ebu";
+ lantiq,output = <1>;
+ lantiq,open-drain = <0>;
+ lantiq,pull = <0>;
+ };
+ mux-1 {
+ lantiq,groups = "nand rdy";
+ lantiq,function = "ebu";
+ lantiq,output = <0>;
+ lantiq,pull = <2>;
+ };
+ };
+
+ nand_cs1_pins: nand-cs1 {
+ mux {
+ lantiq,groups = "nand cs1";
+ lantiq,function = "ebu";
+ lantiq,open-drain = <0>;
+ lantiq,pull = <0>;
+ };
+ };
+
spi_pins: spi {
mux-0 {
lantiq,groups = "spi_di";