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ar71xx: fix ethernet PLL configuration for QCA956x
author
Felix Fietkau
<nbd@nbd.name>
Fri, 17 Feb 2017 10:51:42 +0000
(11:51 +0100)
committer
Felix Fietkau
<nbd@nbd.name>
Fri, 17 Feb 2017 11:16:13 +0000
(12:16 +0100)
QCA956x is configured like AR934x, not like the older chips.
Should fix ethernet hangs when using the WAN port without SGMII
Signed-off-by: Felix Fietkau <nbd@nbd.name>
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
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diff --git
a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 91ff8b2fc904729f9777ecb7ccd8ae75dee141c6..a8b19b68b2a46545fdd3ed6bdf14006f8a741185 100644
(file)
--- a/
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@
-1096,7
+1096,7
@@
void __init ath79_register_eth(unsigned int id)
if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
pdata->set_speed = qca956x_set_speed_sgmii;
else
- pdata->set_speed = a
th79
_set_speed_ge0;
+ pdata->set_speed = a
r934x
_set_speed_ge0;
} else {
pdata->reset_bit = QCA955X_RESET_GE1_MAC |
QCA955X_RESET_GE1_MDIO;