Tegra: memctrl_v2: save TZDRAM settings to secure scratch registers

Save TZDRAM settings for SC7 resume firmware to restore.

SECURITY_BOM:     MC_SECURITY_CFG0_0 = SECURE_RSV55_SCRATCH_0
SECURITY_BOM_HI:  MC_SECURITY_CFG3_0 = SECURE_RSV55_SCRATCH_1
SECURITY_SIZE_MB: MC_SECURITY_CFG1_0 = SECURE_RSV54_SCRATCH_1

Change-Id: I78e891d9ebf576ff2a17ff87cf3aff4030ee11b8
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index bd16b99167628c0a0424620f4c77c4c72bdb3a33..3b662a699e26a0ef6c419bd52e591e3c50c3c7d7 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -622,6 +622,20 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
        tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
        tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
 
+       /*
+        * When TZ encryption enabled,
+        * We need setup TZDRAM before CPU to access TZ Carveout,
+        * otherwise CPU will fetch non-decrypted data.
+        * So save TZDRAM setting for retore by SC7 resume FW.
+        */
+
+       mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_LO,
+                                       tegra_mc_read_32(MC_SECURITY_CFG0_0));
+       mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_HI,
+                                       tegra_mc_read_32(MC_SECURITY_CFG3_0));
+       mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV54_HI,
+                                       tegra_mc_read_32(MC_SECURITY_CFG1_0));
+
        /*
         * MCE propogates the security configuration values across the
         * CCPLEX.

diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index e0eddfd348e8e687ab2ab57c8b1ad4e3746b6759..a394a723933d2af846e5263a05a9d8066501d8de 100644 (file)
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -148,6 +148,9 @@
 #define  SECURE_SCRATCH_RSV11_HI       0x6AC
 #define  SECURE_SCRATCH_RSV53_LO       0x7F8
 #define  SECURE_SCRATCH_RSV53_HI       0x7FC
+#define  SECURE_SCRATCH_RSV54_HI       0x804
+#define  SECURE_SCRATCH_RSV55_LO       0x808
+#define  SECURE_SCRATCH_RSV55_HI       0x80C
 
 /*******************************************************************************
  * Tegra Memory Mapped Control Register Access Bus constants