MISRA fixes for Cortex A75 AMU implementation

Change-Id: I61c9fdfda0c0b3c3ec6249519db23602cf4c2100
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h
index a54e0852ae515ebe9f660f3bdd33dde0023783f6..20f02518aa8a01af6837b23677c1fa738ee5e63b 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a75.h
+++ b/include/lib/cpus/aarch64/cortex_a75.h
@@ -28,9 +28,9 @@
  * CPUAMEVTYPER<n> register and are disabled by default. Platforms may
  * enable this with suitable programming.
  */
-#define CORTEX_A75_AMU_NR_COUNTERS     5
-#define CORTEX_A75_AMU_GROUP0_MASK     0x7
-#define CORTEX_A75_AMU_GROUP1_MASK     (0 << 3)
+#define CORTEX_A75_AMU_NR_COUNTERS     U(5)
+#define CORTEX_A75_AMU_GROUP0_MASK     U(0x7)
+#define CORTEX_A75_AMU_GROUP1_MASK     (U(0) << 3)
 
 #ifndef __ASSEMBLY__
 #include <stdint.h>

diff --git a/lib/cpus/aarch64/cortex_a75_pubsub.c b/lib/cpus/aarch64/cortex_a75_pubsub.c
index 87beca273369447b0c9182bfba63cb623d7dc187..16f62f4722b4d090ec425275072773c3e3b65d59 100644 (file)
--- a/lib/cpus/aarch64/cortex_a75_pubsub.c
+++ b/lib/cpus/aarch64/cortex_a75_pubsub.c
@@ -10,14 +10,14 @@
 
 static void *cortex_a75_context_save(const void *arg)
 {
-       if (midr_match(CORTEX_A75_MIDR))
+       if (midr_match(CORTEX_A75_MIDR) != 0)
                cpuamu_context_save(CORTEX_A75_AMU_NR_COUNTERS);
        return 0;
 }
 
 static void *cortex_a75_context_restore(const void *arg)
 {
-       if (midr_match(CORTEX_A75_MIDR))
+       if (midr_match(CORTEX_A75_MIDR) != 0)
                cpuamu_context_restore(CORTEX_A75_AMU_NR_COUNTERS);
        return 0;
 }

diff --git a/lib/cpus/aarch64/cpuamu.c b/lib/cpus/aarch64/cpuamu.c
index 38c093ac4a184d7122126c38af22915492313b32..b9bad860464375189f0894ee8dc2ec08216db75f 100644 (file)
--- a/lib/cpus/aarch64/cpuamu.c
+++ b/lib/cpus/aarch64/cpuamu.c
@@ -8,11 +8,11 @@
 #include <platform.h>
 #include <pubsub_events.h>
 
-#define CPUAMU_NR_COUNTERS     5
+#define CPUAMU_NR_COUNTERS     5U
 
 struct amu_ctx {
        uint64_t cnts[CPUAMU_NR_COUNTERS];
-       uint16_t mask;
+       unsigned int mask;
 };
 
 static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
@@ -21,7 +21,7 @@ int midr_match(unsigned int cpu_midr)
 {
        unsigned int midr, midr_mask;
 
-       midr = read_midr();
+       midr = (unsigned int)read_midr();
        midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) |
                (MIDR_PN_MASK << MIDR_PN_SHIFT);
        return ((midr & midr_mask) == (cpu_midr & midr_mask));
@@ -30,7 +30,7 @@ int midr_match(unsigned int cpu_midr)
 void cpuamu_context_save(unsigned int nr_counters)
 {
        struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
-       int i;
+       unsigned int i;
 
        assert(nr_counters <= CPUAMU_NR_COUNTERS);
 
@@ -49,7 +49,7 @@ void cpuamu_context_save(unsigned int nr_counters)
 void cpuamu_context_restore(unsigned int nr_counters)
 {
        struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
-       int i;
+       unsigned int i;
 
        assert(nr_counters <= CPUAMU_NR_COUNTERS);