drm/amdgpu: add ib_size/start_alignment interface query

Query the IB alignment requirements from the kernel rather
than hardcoding them in the user mode drivers.

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 12b756e8c6b8253f371ff1c3e80902ff736d3b69..f1e5d87ef1f79dccf95090b9f6150472807a15cc 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -188,6 +188,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                struct drm_amdgpu_info_hw_ip ip = {};
                enum amd_ip_block_type type;
                uint32_t ring_mask = 0;
+               uint32_t ib_start_alignment = 0;
+               uint32_t ib_size_alignment = 0;
 
                if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
                        return -EINVAL;
@@ -197,25 +199,35 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                        type = AMD_IP_BLOCK_TYPE_GFX;
                        for (i = 0; i < adev->gfx.num_gfx_rings; i++)
                                ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
+                       ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+                       ib_size_alignment = 8;
                        break;
                case AMDGPU_HW_IP_COMPUTE:
                        type = AMD_IP_BLOCK_TYPE_GFX;
                        for (i = 0; i < adev->gfx.num_compute_rings; i++)
                                ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
+                       ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+                       ib_size_alignment = 8;
                        break;
                case AMDGPU_HW_IP_DMA:
                        type = AMD_IP_BLOCK_TYPE_SDMA;
                        ring_mask = adev->sdma[0].ring.ready ? 1 : 0;
                        ring_mask |= ((adev->sdma[1].ring.ready ? 1 : 0) << 1);
+                       ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+                       ib_size_alignment = 1;
                        break;
                case AMDGPU_HW_IP_UVD:
                        type = AMD_IP_BLOCK_TYPE_UVD;
                        ring_mask = adev->uvd.ring.ready ? 1 : 0;
+                       ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+                       ib_size_alignment = 8;
                        break;
                case AMDGPU_HW_IP_VCE:
                        type = AMD_IP_BLOCK_TYPE_VCE;
                        for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++)
                                ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
+                       ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+                       ib_size_alignment = 8;
                        break;
                default:
                        return -EINVAL;
@@ -228,6 +240,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                                ip.hw_ip_version_minor = adev->ip_blocks[i].minor;
                                ip.capabilities_flags = 0;
                                ip.available_rings = ring_mask;
+                               ip.ib_start_alignment = ib_start_alignment;
+                               ip.ib_size_alignment = ib_size_alignment;
                                break;
                        }
                }

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index e24cc2e318df15ad2887c61f64d914a9ae98c5d2..3af5bd0e23a8260cb3b4e37bb5e3e3629117a80a 100644 (file)
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -583,6 +583,10 @@ struct drm_amdgpu_info_hw_ip {
        uint32_t  hw_ip_version_minor;
        /** Capabilities */
        uint64_t  capabilities_flags;
+       /** command buffer address start alignment*/
+       uint32_t  ib_start_alignment;
+       /** command buffer size alignment*/
+       uint32_t  ib_size_alignment;
        /** Bitmask of available rings. Bit 0 means ring 0, etc. */
        uint32_t  available_rings;
        uint32_t  _pad;