Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO

This patch moves the TZDRAM base address to SCRATCH55_LO due
to security concerns. The HI and LO address bits are packed
into SCRATCH55_LO for the warmboot firmware to restore.
SCRATCH54_HI is still being used for backward compatibility,
but would be removed eventually.

The scratch registers are populated as:
* RSV55_0 = CFG1[12:0] | CFG0[31:20]
* RSV55_1 = CFG3[1:0]
* RSV54_1 = CFG1[12:0]

Change-Id: Idc20d165d8117488010fcc8dfd946f7ad475da58
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index 3d53644c67d15df9248f24268a04f83fe31c3f15..cfa95818e9352c64122b624b1b31c289870bf1fa 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -444,6 +444,8 @@ void tegra_memctrl_restore_settings(void)
  */
 void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
 {
+       uint32_t val;
+
        /*
         * Setup the Memory controller to allow only secure accesses to
         * the TZDRAM carveout
@@ -458,15 +460,20 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
         * When TZ encryption enabled,
         * We need setup TZDRAM before CPU to access TZ Carveout,
         * otherwise CPU will fetch non-decrypted data.
-        * So save TZDRAM setting for retore by SC7 resume FW.
+        * So save TZDRAM setting for restore by SC7 resume FW.
+        * Scratch registers map:
+        *  RSV55_0 = CFG1[12:0] | CFG0[31:20]
+        *  RSV55_1 = CFG3[1:0]
         */
 
-       mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_LO,
-                                       tegra_mc_read_32(MC_SECURITY_CFG0_0));
-       mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_HI,
-                                       tegra_mc_read_32(MC_SECURITY_CFG3_0));
-       mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV54_HI,
-                                       tegra_mc_read_32(MC_SECURITY_CFG1_0));
+       val = tegra_mc_read_32(MC_SECURITY_CFG1_0) & MC_SECURITY_SIZE_MB_MASK;
+       mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV54_HI, val);
+
+       val |= tegra_mc_read_32(MC_SECURITY_CFG0_0) & MC_SECURITY_BOM_MASK;
+       mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_LO, val);
+
+       val = tegra_mc_read_32(MC_SECURITY_CFG3_0) & MC_SECURITY_BOM_HI_MASK;
+       mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_HI, val);
 
        /*
         * MCE propagates the security configuration values across the

diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index 19d1250b3e58a5ef0309f042dfef819bbfa2ab04..20a799475fd874b8478b31f6baacdf5b2ea74647 100644 (file)
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -141,6 +141,10 @@
 #define MC_SECURITY_CFG1_0             U(0x74)
 #define MC_SECURITY_CFG3_0             U(0x9BC)
 
+#define MC_SECURITY_BOM_MASK           (U(0xFFF) << 20)
+#define MC_SECURITY_SIZE_MB_MASK       (U(0x1FFF) << 0)
+#define MC_SECURITY_BOM_HI_MASK                (U(0x3) << 0)
+
 /* Video Memory carveout configuration registers */
 #define MC_VIDEO_PROTECT_BASE_HI       U(0x978)
 #define MC_VIDEO_PROTECT_BASE_LO       U(0x648)