drm/i915: Add engine reset count to error state
authorMichel Thierry <michel.thierry@intel.com>
Tue, 20 Jun 2017 09:57:48 +0000 (10:57 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 20 Jun 2017 20:00:22 +0000 (21:00 +0100)
Driver maintains count of how many times a given engine is reset, useful to
capture this in error state also. It gives an idea of how engine is coping
up with the workloads it is executing before this error state.

A follow-up patch will provide this information in debugfs.

v2: s/engine_reset/reset_engine/ (Chris)
    Define count as unsigned int (Tvrtko)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170615201828.23144-7-michel.thierry@intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/20170620095751.13127-7-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gpu_error.c

index 2ecac000e5dadd8074df4ec3ce5715934950e11d..d35a114c46ede0a9690e38ae45d0c0803c708f40 100644 (file)
@@ -1971,7 +1971,10 @@ int i915_reset_engine(struct intel_engine_cs *engine)
         * process to program RING_MODE, HWSP and re-enable submission.
         */
        ret = engine->init_hw(engine);
+       if (ret)
+               goto out;
 
+       error->reset_engine_count[engine->id]++;
 out:
        return ret;
 }
index 152e30750dd49aa98179a24c34305598985d79d9..90cc63e5ced8c0518acb3b98f3bbddf4c1504db1 100644 (file)
@@ -917,6 +917,7 @@ struct i915_gpu_state {
                enum intel_engine_hangcheck_action hangcheck_action;
                struct i915_address_space *vm;
                int num_requests;
+               u32 reset_count;
 
                /* position of active request inside the ring */
                u32 rq_head, rq_post, rq_tail;
@@ -1567,6 +1568,9 @@ struct i915_gpu_error {
 #define I915_WEDGED            (BITS_PER_LONG - 1)
 #define I915_RESET_ENGINE      (I915_WEDGED - I915_NUM_ENGINES)
 
+       /** Number of times an engine has been reset */
+       u32 reset_engine_count[I915_NUM_ENGINES];
+
        /**
         * Waitqueue to signal when a hang is detected. Used to for waiters
         * to release the struct_mutex for the reset to procede.
@@ -3474,6 +3478,12 @@ static inline u32 i915_reset_count(struct i915_gpu_error *error)
        return READ_ONCE(error->reset_count);
 }
 
+static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
+                                         struct intel_engine_cs *engine)
+{
+       return READ_ONCE(error->reset_engine_count[engine->id]);
+}
+
 struct drm_i915_gem_request *
 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
index e18f350bc364253b7228c3d913f1797ce7b1f919..ae70283470a6c7b9ee60c22f7e652d9abfe697fb 100644 (file)
@@ -463,6 +463,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
        err_printf(m, "  hangcheck action timestamp: %lu, %u ms ago\n",
                   ee->hangcheck_timestamp,
                   jiffies_to_msecs(jiffies - ee->hangcheck_timestamp));
+       err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 
        error_print_request(m, "  ELSP[0]: ", &ee->execlist[0]);
        error_print_request(m, "  ELSP[1]: ", &ee->execlist[1]);
@@ -1236,6 +1237,8 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
        ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
        ee->hangcheck_action = engine->hangcheck.action;
        ee->hangcheck_stalled = engine->hangcheck.stalled;
+       ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
+                                                 engine);
 
        if (USES_PPGTT(dev_priv)) {
                int i;