drm/i915/tgl: Add note about Wa_1409142259
authorJosé Roberto de Souza <jose.souza@intel.com>
Thu, 27 Feb 2020 22:00:58 +0000 (14:00 -0800)
committerJosé Roberto de Souza <jose.souza@intel.com>
Mon, 2 Mar 2020 20:00:42 +0000 (12:00 -0800)
Different issues with the same fix, so justing adding
Wa_1409142259, Wa_1409252684, Wa_1409217633, Wa_1409207793,
Wa_1409178076 and 1408979724 to the comment so other devs can check if
this Was were implemetend with a simple grep.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200227220101.321671-8-jose.souza@intel.com
drivers/gpu/drm/i915/gt/intel_workarounds.c

index 0cdd3c50e0ae7b35e093750360122303e23dd767..ba02657634840d97d2149aba19388ecd929ab2ac 100644 (file)
@@ -580,7 +580,15 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
                                     struct i915_wa_list *wal)
 {
-       /* Wa_1409142259:tgl */
+       /*
+        * Wa_1409142259:tgl
+        * Wa_1409347922:tgl
+        * Wa_1409252684:tgl
+        * Wa_1409217633:tgl
+        * Wa_1409207793:tgl
+        * Wa_1409178076:tgl
+        * Wa_1408979724:tgl
+        */
        WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
                          GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);