powerpc/64s: Power9 has no LPCR[VRMASD] field so don't set it

Power9/ISAv3 has no VRMASD field in LPCR, we shouldn't be setting reserved bits,
so don't set them on Power9.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index 1fce4ddd2e6c6f254d917545380b21f05253281f..10cb2896b2ae59641741bcd8fb4c322252b8556d 100644 (file)
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -30,7 +30,7 @@ _GLOBAL(__setup_cpu_power7)
        mtspr   SPRN_LPID,r0
        mfspr   r3,SPRN_LPCR
        li      r4,(LPCR_LPES1 >> LPCR_LPES_SH)
-       bl      __init_LPCR
+       bl      __init_LPCR_ISA206
        bl      __init_tlb_power7
        mtlr    r11
        blr
@@ -44,7 +44,7 @@ _GLOBAL(__restore_cpu_power7)
        mtspr   SPRN_LPID,r0
        mfspr   r3,SPRN_LPCR
        li      r4,(LPCR_LPES1 >> LPCR_LPES_SH)
-       bl      __init_LPCR
+       bl      __init_LPCR_ISA206
        bl      __init_tlb_power7
        mtlr    r11
        blr
@@ -62,7 +62,7 @@ _GLOBAL(__setup_cpu_power8)
        mfspr   r3,SPRN_LPCR
        ori     r3, r3, LPCR_PECEDH
        li      r4,0 /* LPES = 0 */
-       bl      __init_LPCR
+       bl      __init_LPCR_ISA206
        bl      __init_HFSCR
        bl      __init_tlb_power8
        bl      __init_PMU_HV
@@ -84,7 +84,7 @@ _GLOBAL(__restore_cpu_power8)
        mfspr   r3,SPRN_LPCR
        ori     r3, r3, LPCR_PECEDH
        li      r4,0 /* LPES = 0 */
-       bl      __init_LPCR
+       bl      __init_LPCR_ISA206
        bl      __init_HFSCR
        bl      __init_tlb_power8
        bl      __init_PMU_HV
@@ -108,7 +108,7 @@ _GLOBAL(__setup_cpu_power9)
        LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
        andc    r3, r3, r4
        li      r4,0 /* LPES = 0 */
-       bl      __init_LPCR
+       bl      __init_LPCR_ISA300
        bl      __init_HFSCR
        bl      __init_tlb_power9
        bl      __init_PMU_HV
@@ -132,7 +132,7 @@ _GLOBAL(__restore_cpu_power9)
        LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
        andc    r3, r3, r4
        li      r4,0 /* LPES = 0 */
-       bl      __init_LPCR
+       bl      __init_LPCR_ISA300
        bl      __init_HFSCR
        bl      __init_tlb_power9
        bl      __init_PMU_HV
@@ -150,7 +150,7 @@ __init_hvmode_206:
        std     r5,CPU_SPEC_FEATURES(r4)
        blr
 
-__init_LPCR:
+__init_LPCR_ISA206:
        /* Setup a sane LPCR:
         *   Called with initial LPCR in R3 and desired LPES 2-bit value in R4
         *
@@ -163,6 +163,11 @@ __init_LPCR:
         *
         * Other bits untouched for now
         */
+       li      r5,0x10
+       rldimi  r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
+
+       /* POWER9 has no VRMASD */
+__init_LPCR_ISA300:
        rldimi  r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
        ori     r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
        li      r5,4
@@ -170,8 +175,6 @@ __init_LPCR:
        clrrdi  r3,r3,1         /* clear HDICE */
        li      r5,4
        rldimi  r3,r5, LPCR_VC_SH, 0
-       li      r5,0x10
-       rldimi  r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
        mtspr   SPRN_LPCR,r3
        isync
        blr