--- /dev/null
+From 2038e0416518b30bb40857fbafa3733a6bae93ca Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
+Date: Tue, 26 May 2020 13:03:24 +0200
+Subject: [PATCH] MIPS: BCM63xx: fix 6328 boot selection bit
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+MISC_STRAP_BUS_BOOT_SEL_SHIFT is 18 according to Broadcom's GPL source code.
+
+Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1367,8 +1367,8 @@
+ #define MISC_STRAPBUS_6328_REG 0x240
+ #define STRAPBUS_6328_FCVO_SHIFT 7
+ #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
+-#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
+-#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
++#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 18)
++#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 18)
+
+ /*************************************************************************
+ * _REG relative to RSET_PCIE
+++ /dev/null
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -1367,8 +1367,8 @@
- #define MISC_STRAPBUS_6328_REG 0x240
- #define STRAPBUS_6328_FCVO_SHIFT 7
- #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
--#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
--#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
-+#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 18)
-+#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 18)
-
- /*************************************************************************
- * _REG relative to RSET_PCIE