Changes for U-Boot 1.0.2:
======================================================================
+* Patch by Stephen Williams, 19 March 2004
+ Increase speed of sector reads from SystemACE,
+ shorten poll timeout and remove a useless reset
+
+* Patch by Tolunay Orkun, 19 Mar 2004:
+ Make GigE PHY 1000Mbps Speed/Duplex detection conditional
+ (CONFIG_PHY_GIGE)
+
+* Patch by Brad Kemp, 18 Mar 2004:
+ prevent machine checks during a PCI scan
+
+* Patch by Pierre Aubert, 18 Mar 2004:
+ Fix string cleaning in IDE identification
+
* Patch by Pierre Aubert, 18 Mar 2004:
- Unify video mode handling for Chips & Technologies 69000 Video
chip and Silicon Motion SMI 712/710/810 Video chip
/* Write sector count | ReadMemCardData. */
ace_writew((trans&0xff) | 0x0300, 0x14);
- /* CONTROLREG = CFGRESET|LOCKREQ */
- ace_writew(0x0082, 0x18);
-
retry = trans * 16;
while (retry > 0) {
int idx;
/* Wait for buffer to become ready. */
while (! (ace_readw(0x04) & 0x0020)) {
- udelay(1000);
+ udelay(100);
}
/* Read 16 words of 2bytes from the sector buffer. */
unsigned char *end, *last;
last = dst;
- end = src + len;
+ end = src + len - 1;
/* reserve space for '\0' */
if (len < 2)
{
unsigned short reg;
+#if defined(CONFIG_PHY_GIGE)
if (miiphy_read (addr, PHY_1000BTSR, ®)) {
printf ("PHY 1000BT Status read failed\n");
} else {
}
}
}
+#endif /* CONFIG_PHY_GIGE */
if (miiphy_read (addr, PHY_ANLPAR, ®)) {
puts ("PHY speed1 read failed, assuming 10bT\n");
{
unsigned short reg;
-
+#if defined(CONFIG_PHY_GIGE)
if (miiphy_read (addr, PHY_1000BTSR, ®)) {
printf ("PHY 1000BT Status read failed\n");
} else {
}
}
}
+#endif /* CONFIG_PHY_GIGE */
if (miiphy_read (addr, PHY_ANLPAR, ®)) {
puts ("PHY duplex read failed, assuming half duplex\n");
dump_pci();
#endif
/* clear the error in the error status register */
- if(immap->im_pci.pci_esr && cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) {
+ if(immap->im_pci.pci_esr & cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) {
immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP);
return;
}
#define CONFIG_PHY2_ADDR 0x10
#define CONFIG_PHY3_ADDR 0x18
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 10.1.2.3
#define CONFIG_ETHADDR 00:04:AC:E3:28:8A
#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */
#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */
#define CONFIG_NET_MULTI 1
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \