static struct resource resources[] =
{
[0] = {
- .name = "dwc_otg_membase",
- .start = LTQ_USB_IOMEM_BASE,
- .end = LTQ_USB_IOMEM_BASE + LTQ_USB_IOMEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
+ .name = "dwc_otg_membase",
+ .start = LTQ_USB_IOMEM_BASE,
+ .end = LTQ_USB_IOMEM_BASE + LTQ_USB_IOMEM_SIZE - 1,
+ .flags = IORESOURCE_MEM,
},
[1] = {
- .name = "dwc_otg_irq",
- .flags = IORESOURCE_IRQ,
+ .name = "dwc_otg_irq",
+ .flags = IORESOURCE_IRQ,
},
};
static struct platform_device platform_dev = {
.name = "dwc_otg",
.dev = {
- .dma_mask = &dwc_dmamask,
+ .dma_mask = &dwc_dmamask,
},
.resource = resources,
.num_resources = ARRAY_SIZE(resources),
void __init
ltq_register_rt2x00(const char *firmware)
{
- rt2x00_pdata.eeprom_file_name = kstrdup(firmware, GFP_KERNEL);
+ rt2x00_pdata.eeprom_file_name = kstrdup(firmware, GFP_KERNEL);
ltqpci_plat_dev_init = rt2x00_pci_plat_dev_init;
}
.parts = arv_partitions,
};
-static void arv_load_nor(unsigned int max)
-{
-#define UBOOT_MAGIC 0x27051956
-
- int i;
- int sector = -1;
-
- if (ltq_brn_boot) {
- if (max == 0x800000)
- ltq_register_nor(&arv75xx_brnboot_flash_data);
- else
- ltq_register_nor(&arv45xx_brnboot_flash_data);
- return;
- }
-
- for (i = 1; i < 4 && sector < 0; i++) {
- unsigned int uboot_magic;
- memcpy_fromio(&uboot_magic, (void *)KSEG1ADDR(LTQ_FLASH_START) + (i * 0x10000), 4);
- if (uboot_magic == UBOOT_MAGIC)
- sector = i;
- }
-
- if (sector < 0)
- return;
-
- arv_partitions[0].size = arv_partitions[1].offset = (sector - 1) * 0x10000;
- arv_partitions[2].offset = arv_partitions[0].size + 0x10000;
- arv_partitions[2].size = max - arv_partitions[2].offset - 0x10000;
- arv_partitions[3].offset = max - 0x10000;
- ltq_register_nor(&arv_flash_data);
-}
-
static struct ltq_pci_data ltq_pci_data = {
- .clock = PCI_CLOCK_EXT,
- .gpio = PCI_GNT1 | PCI_REQ1,
- .irq = {
+ .clock = PCI_CLOCK_EXT,
+ .gpio = PCI_GNT1 | PCI_REQ1,
+ .irq = {
[14] = INT_NUM_IM0_IRL0 + 22,
},
};
#define ARV4525PW_PHYRESET 13
#define ARV4525PW_RELAY 31
-static struct gpio arv4525pw_gpios[] __initdata = {
- { ARV4525PW_PHYRESET, GPIOF_OUT_INIT_HIGH, "phyreset" },
- { ARV4525PW_RELAY, GPIOF_OUT_INIT_HIGH, "relay" },
+static struct gpio
+arv4525pw_gpios[] __initdata = {
+ { ARV4525PW_PHYRESET, GPIOF_OUT_INIT_HIGH, "phyreset" },
+ { ARV4525PW_RELAY, GPIOF_OUT_INIT_HIGH, "relay" },
};
},
};
-static void
+static void __init
+arv_load_nor(unsigned int max)
+{
+#define UBOOT_MAGIC 0x27051956
+
+ int i;
+ int sector = -1;
+
+ if (ltq_brn_boot) {
+ if (max == 0x800000)
+ ltq_register_nor(&arv75xx_brnboot_flash_data);
+ else
+ ltq_register_nor(&arv45xx_brnboot_flash_data);
+ return;
+ }
+
+ for (i = 1; i < 4 && sector < 0; i++) {
+ unsigned int uboot_magic;
+ memcpy_fromio(&uboot_magic, (void *)KSEG1ADDR(LTQ_FLASH_START) + (i * 0x10000), 4);
+ if (uboot_magic == UBOOT_MAGIC)
+ sector = i;
+ }
+
+ if (sector < 0)
+ return;
+
+ arv_partitions[0].size = arv_partitions[1].offset = (sector - 1) * 0x10000;
+ arv_partitions[2].offset = arv_partitions[0].size + 0x10000;
+ arv_partitions[2].size = max - arv_partitions[2].offset - 0x10000;
+ arv_partitions[3].offset = max - 0x10000;
+ ltq_register_nor(&arv_flash_data);
+}
+
+static void __init
arv_register_ethernet(unsigned int mac_addr)
{
memcpy_fromio(<q_eth_data.mac.sa_data,
static u16 arv_ath9k_eeprom_data[ATH9K_PLAT_EEP_MAX_WORDS];
static u8 arv_athxk_eeprom_mac[6];
-void __init
+static void __init
arv_register_ath5k(unsigned int ath_addr, unsigned int mac_addr)
{
int i;
}
}
-void __init
+static void __init
arv_register_ath9k(unsigned int ath_addr, unsigned int mac_addr)
{
int i;
#define ARV3527P_MAC_ADDR 0x3f0016
ltq_register_gpio_stp();
- //ltq_add_device_gpio_leds(arv3527p_gpio_leds, ARRAY_SIZE(arv3527p_gpio_leds));
+ // ltq_add_device_gpio_leds(arv3527p_gpio_leds, ARRAY_SIZE(arv3527p_gpio_leds));
arv_load_nor(0x400000);
arv_register_ethernet(ARV3527P_MAC_ADDR);
}
xway_register_dwc(ARV452CPW_USB);
arv_register_ethernet(ARV452CPW_MAC_ADDR);
arv_register_ath5k(ARV452CPW_ATH_ADDR, ARV452CPW_MAC_ADDR);
- ltq_register_ath5k(arv_ath5k_eeprom_data, arv_athxk_eeprom_mac);
+ ltq_register_ath5k(arv_ath5k_eeprom_data, arv_athxk_eeprom_mac);
gpio_request(ARV452CPW_SWITCH_RESET, "switch");
gpio_set_value(ARV452CPW_SWITCH_RESET, 1);
.mii_mode = -1, /* use EPHY */
};
-static void __init easy50601_init(void)
+static void __init
+easy50601_init(void)
{
ltq_register_nor(&easy50601_flash_data);
ltq_register_etop(<q_eth_data);
.mii_mode = PHY_INTERFACE_MODE_MII,
};
-static void __init easy50712_init(void)
+static void __init
+easy50712_init(void)
{
ltq_register_gpio_stp();
ltq_register_nor(&easy50712_flash_data);
}
MIPS_MACHINE(LTQ_MACH_EASY50712,
- "EASY50712",
- "EASY50712 Eval Board",
- easy50712_init);
+ "EASY50712",
+ "EASY50712 Eval Board",
+ easy50712_init);
};
static struct ltq_pci_data ltq_pci_data = {
- .clock = PCI_CLOCK_INT,
- .gpio = PCI_GNT1 | PCI_REQ1,
- .irq = {
+ .clock = PCI_CLOCK_INT,
+ .gpio = PCI_GNT1 | PCI_REQ1,
+ .irq = {
[14] = INT_NUM_IM0_IRL0 + 22,
},
};
static int usb_pins[2] = { 50, 51 };
-static void __init fritz7320_init(void)
+static void __init
+fritz7320_init(void)
{
ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL,
ARRAY_SIZE(fritz7320_gpio_keys), fritz7320_gpio_keys);
}
MIPS_MACHINE(LANTIQ_MACH_FRITZ7320,
- "FRITZ7320",
- "FRITZ!BOX 7320",
- fritz7320_init);
+ "FRITZ7320",
+ "FRITZ!BOX 7320",
+ fritz7320_init);
};
static struct spi_board_info spi_flash __initdata = {
- .modalias = "m25p80",
- .bus_num = 0,
- .chip_select = 0,
- .max_speed_hz = 10 * 1000 * 1000,
- .mode = SPI_MODE_3,
+ .modalias = "m25p80",
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 10 * 1000 * 1000,
+ .mode = SPI_MODE_3,
.chip_select = 0,
.controller_data = (void *) SPI_GPIO_CS0,
- .platform_data = &spi_flash_data
+ .platform_data = &spi_flash_data
};
static void __init
platform_device_register(&spi_gpio_device);
}
-static void __init fritz3370_init(void)
+static void __init
+fritz3370_init(void)
{
spi_gpio_init();
platform_device_register_simple("pcie-xway", 0, NULL, 0);
}
MIPS_MACHINE(LANTIQ_MACH_FRITZ3370,
- "FRITZ3370",
- "FRITZ!BOX 3370",
- fritz3370_init);
+ "FRITZ3370",
+ "FRITZ!BOX 3370",
+ fritz3370_init);
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/input.h>
-#include <linux/ath5k_platform.h>
#include <linux/pci.h>
#include <linux/phy.h>
#include <linux/io.h>
static u8 ltq_ethaddr[6] = { 0 };
-static int __init setup_ethaddr(char *str)
+static int __init
+setup_ethaddr(char *str)
{
if (!mac_pton(str, ltq_ethaddr))
memset(ltq_ethaddr, 0, 6);
SX762,
SX763,
};
-static u8 board = SX763;
+static u8 board __initdata = SX763;
-static int __init setup_board(char *str)
+static int __init
+setup_board(char *str)
{
if (!strcmp(str, "sx761"))
board = SX761;
.mii_mode = PHY_INTERFACE_MODE_MII,
};
-static void __init gigasx76x_init(void)
+static void __init
+gigasx76x_init(void)
{
#define GIGASX76X_USB 29
#ifndef _MACH_GIGASX76X_H__
#define _MACH_GIGASX76X_H__
-static u16 sx763_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS]=
+#include <linux/ath5k_platform.h>
+
+static u16 sx763_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS] =
{
0x0013,0x168c,0x0200,0x0001,0x0000,0x5001,0x0000,0x2051,0x2051,0x1c0a,0x0100,
0x0000,0x01c2,0x0002,0xc606,0x0001,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,
0xffff,0xffff};
-static u16 sx762_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS]=
+static u16 sx762_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS] =
{
0x001a,0x168c,0x0200,0x0001,0x0000,0x5001,0x0000,0x2051,0x2051,0x1c0a,0x0100,
0x0000,0x01c2,0x0002,0xc606,0x0001,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
};
static struct ltq_pci_data ltq_pci_data = {
- .clock = PCI_CLOCK_INT,
- .gpio = PCI_GNT1 | PCI_REQ1,
- .irq = {
+ .clock = PCI_CLOCK_INT,
+ .gpio = PCI_GNT1 | PCI_REQ1,
+ .irq = {
[14] = INT_NUM_IM0_IRL0 + 22,
},
};
---help---
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
-@@ -867,6 +867,169 @@ static int refresh_rootfs_split(struct m
+@@ -867,6 +867,168 @@ static int refresh_rootfs_split(struct m
}
#endif /* CONFIG_MTD_ROOTFS_SPLIT */
-+
+#ifdef CONFIG_MTD_UIMAGE_SPLIT
+static unsigned long find_uimage_size(struct mtd_info *mtd,
+ unsigned long offset)
+}
+
+static unsigned long find_brnimage_size(struct mtd_info *mtd,
-+ unsigned long offset)
++ unsigned long offset)
+{
+ unsigned long buf[4];
+ // Assume at most 2MB of kernel image
/*
* This function, given a master MTD object and a partition table, creates
* and registers slave MTD objects which are bound to the master according to
-@@ -883,7 +1046,7 @@ int add_mtd_partitions(struct mtd_info *
+@@ -883,7 +1045,7 @@ int add_mtd_partitions(struct mtd_info *
struct mtd_part *slave;
uint64_t cur_offset = 0;
int i;
int ret;
#endif
-@@ -900,6 +1063,17 @@ int add_mtd_partitions(struct mtd_info *
+@@ -900,6 +1062,15 @@ int add_mtd_partitions(struct mtd_info *
add_mtd_device(&slave->mtd);
+ if (!strcmp(parts[i].name, "linux")) {
+ ret = split_uimage(master, &parts[i]);
+
-+ if (ret) {
-+ printk(KERN_WARNING
-+ "Can't split linux partition\n");
-+ }
++ if (ret)
++ printk(KERN_WARNING "Can't split linux partition\n");
+ }
+#endif
+
+void __init
+ltq_register_tapi(void)
+{
-+#define CP1_SIZE (1 << 20)
++#define CP1_SIZE (1 << 20)
+ dma_addr_t dma;
+ cp1_base =
+ (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC));
+/* ebu */
+static struct resource ltq_ebu_resource =
+{
-+ .name = "gpio_ebu",
-+ .start = LTQ_EBU_GPIO_START,
-+ .end = LTQ_EBU_GPIO_START + LTQ_EBU_GPIO_SIZE - 1,
-+ .flags = IORESOURCE_MEM,
++ .name = "gpio_ebu",
++ .start = LTQ_EBU_GPIO_START,
++ .end = LTQ_EBU_GPIO_START + LTQ_EBU_GPIO_SIZE - 1,
++ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device ltq_ebu =
+{
-+ .name = "ltq_ebu",
-+ .resource = <q_ebu_resource,
-+ .num_resources = 1,
++ .name = "ltq_ebu",
++ .resource = <q_ebu_resource,
++ .num_resources = 1,
+};
+
+void __init
+
+static struct resource ltq_spi_resources[] = {
+ {
-+ .start = LTQ_SSC_BASE_ADDR,
-+ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
-+ .flags = IORESOURCE_MEM,
++ .start = LTQ_SSC_BASE_ADDR,
++ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
++ .flags = IORESOURCE_MEM,
+ },
+ IRQ_RES(spi_tx, LTQ_SSC_TIR),
+ IRQ_RES(spi_rx, LTQ_SSC_RIR),
+
+static struct resource ltq_spi_resources_ar9[] = {
+ {
-+ .start = LTQ_SSC_BASE_ADDR,
-+ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
-+ .flags = IORESOURCE_MEM,
++ .start = LTQ_SSC_BASE_ADDR,
++ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
++ .flags = IORESOURCE_MEM,
+ },
+ IRQ_RES(spi_tx, LTQ_SSC_TIR_AR9),
+ IRQ_RES(spi_rx, LTQ_SSC_RIR_AR9),
+
+static struct resource ltq_spi_resources_ase[] = {
+ {
-+ .start = LTQ_SSC_BASE_ADDR,
-+ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
-+ .flags = IORESOURCE_MEM,
++ .start = LTQ_SSC_BASE_ADDR,
++ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
++ .flags = IORESOURCE_MEM,
+ },
+ IRQ_RES(spi_tx, LTQ_SSC_TIR_ASE),
+ IRQ_RES(spi_rx, LTQ_SSC_RIR_ASE),