drm/i915: Don't do PM5/DDR DVFS with multiple pipes

Enabling PM5/DDR DVFS with multiple active pipes isn't a validated
configuration. It does seem to work most of the time at least, but
there is clearly an additional risk of underruns, so let's not play
with fire.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a023b40c046b77be2c13d3cf31cf79ca033ca1eb..16ca34fb5380dba0f860ba6e9310225abf77f19c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1327,6 +1327,9 @@ static void vlv_merge_wm(struct drm_device *dev,
        if (num_active_crtcs != 1)
                wm->cxsr = false;
 
+       if (num_active_crtcs > 1)
+               wm->level = VLV_WM_LEVEL_PM2;
+
        for_each_intel_crtc(dev, crtc) {
                struct vlv_wm_state *wm_state = &crtc->wm_state;
                enum pipe pipe = crtc->pipe;